586
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
bc
Branch Conditional
Description
target
is a 32-bit operand that specifies a displacement to the branch-target address. The
assembler sets the instruction-opcode BD field to the value of
target
16:29
.
The next instruction address (NIA) is the effective address of the branch target. The NIA is
calculated by adding the displacement to a base address, which are formed as follows:
•
The displacement is obtained by concatenating two 0-bits to the right of the BD field
and sign-extending the result to 32 bits.
•
If the AA field contains 0 (relative addressing), the branch-instruction address is used
as the base address. The branch-instruction address is the current instruction address
(CIA).
•
If the AA field contains 1 (absolute addressing), the base address is 0.
Program flow is transferred to the NIA. If the LK field contains 1, then the address of the
instruction following the branch instruction (CIA + 4) is loaded into the LR.
The BO field specifies whether the branch is conditional on the contents of the CTR and/or
the CR registers and how those conditions are tested. The BO field also specifies whether
the CTR is decremented. The encoding of the BO field is described in
. The BI field specifies which CR bit is tested if the branch is conditional
on the CR register.
Simplified mnemonics defined for this instruction are described in the following sections:
•
?<Fill in list after appendix is built>
Pseudocode
if BO
2
=
0 then
CTR
←
CTR
−
1
CTR_cond_met
←
BO
2
∨
((CTR
≠
0)
⊕
BO
3
))
CR_cond_met
←
BO
0
∨
(CR
B
I
=
BO
1
)
if CTR_cond_met
∧
CR_cond_met
then if AA
=
1
then NIA
←
EXTS(BD
||
0b00)
else
NIA
←
CIA + EXTS(BD
||
0b00)
else
NIA
←
CIA + 4
if LK
=
1 then
(LR)
←
CIA + 4
Registers Altered
•
CTR if BO
2
=
0.
bc
BO, BI, target
(AA=0, LK=0)
bca
BO, BI, target
(AA=1, LK=0)
bcl
BO, BI, target
(AA=0, LK=1)
bcla
BO, BI, target
(AA=1, LK=1)
B Instruction Form
16
BO
BI
BD
AA LK
0
6
11
16
30 31
