March 2002 Release
733
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
Exceptions
•
Data storage—if the access is prevented by zone protection when data relocation is
enabled.
-
No-access-allowed zone protection applies only to accesses in user mode.
-
Read-only zone protection applies to user and privileged modes.
•
Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
If XER[TBC]
=
0, data-storage and data TLB-miss exceptions do not occur. However, a data
machine-check exception can occur when XER[TBC]
=
0 if the following conditions are true:
•
The instruction access passes all protection checks.
•
The data address is cachable.
•
Access of the data address causes a data-cacheline fill request due to a miss.
•
The data-cacheline fill request encounters some form of bus error.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
