Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 607
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
dcbf
Data Cache Block Flush
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
If EA is cached by the data cache, the corresponding data cacheline is invalidated. If the
data cacheline is marked as modified, the contents of the cacheline are written (flushed) to
main memory prior to the invalidation. The flush operation is performed whether or not
the corresponding storage attribute indicates EA is cachable. If EA is not cached, no
operation is performed.
Pseudocode
EA
←
( r A|0) + ( r B)
Flush data cacheline corresponding to EA
Registers Altered
• None.
Exceptions
• Data storage—if the access is prevented by no-access-allowed zone protection. This
only applies to accesses in user mode when data relocation is enabled.
• Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
This instruction is considered a “load” with respect to the above data-access exceptions. It
is considered a “store” with respect to data address-compare (DAC) debug exceptions.
Debug exceptions can occur as a result of executing this instruction.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• Reserved bits containing a non-zero value.
dcbf r A, r B
X Instruction Form
31 0 0 0 0 0 r A r B 86 0
0 6 1
1 1
6 2
1 3
1