Xilinx Virtex-II Pro PPC405, User Manual

Page: 71 / 562

March 2002 Release www.xilinx.com 379
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Integer Load and Store Instructions
R
Figure 3-17 shows how an effective address is generated when using register-indirect with
immediate-index addressing.
Register-Indirect with Index
Load and store instructions using this addressing mode contain two general-purpose
register operands,
r A and r B. The contents of these two registers are added to generate the
effective address. If the r A instruction field is 0 (specifying r 0), a value of zero—rather than
the contents of r 0—is added to r B. The option to specify r A or 0 is shown in the instruction
description as (
r
A|0).
Figure 3-18 shows how an effective address is generated when using register-indirect with
index addressing.
Figure 3-17: Register-Indirect with Immediate-Index Addressing
UG011_02_033101
Instruction Encoding
Opcode r D/ r S r A
0 6 11 16
16
31
d
0 31
Effective Address
0 31
+
( r A)
0 31
0000 0000 0000 0000 0000 0000 0000 0000
0 31
r A
=
0?
Yes
No
d
Sign Extension