510
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 7:
Exceptions and Interrupts
R
Alignment Interrupt (0x0600)
Interrupt Classification
•
Noncritical—return using the
rfi
instruction.
•
Synchronous.
•
Precise.
Description
Alignment exceptions are caused by the following memory accesses:
•
Executing a
dcbz
instruction with an operand located in non-cacheable or write-
through memory.
•
Executing an
lwarx
instruction with an operand that is not aligned on a word
boundary.
•
Executing an
stwcx.
instruction with an operand that is not aligned on a word
boundary.
•
From privileged mode (MSR[PR]
=
0), executing a
dcread
instruction with an operand
that is not aligned on a word boundary.
Software cannot disable alignment interrupts.
Affected Registers
Register
Value After Interrupt
SRR0
Loaded with the effective address of the instruction that caused the alignment
exception.
SRR1
Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2
Not used.
SRR3
ESR
DEAR
Loaded with the effective address of the operand that caused the alignment
exception.
MSR
[AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR]
←
0.
[CE, ME, DE]
←
Unchanged.
