Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 517
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Interrupt Reference
R
Fixed-Interval Timer Interrupt (0x1010)
Interrupt Classification
• Noncritical—return using the rfi instruction.
• Asynchronous.
• Precise.
Description
A fixed-interval timer exception is caused by a time-out on the fixed-interval timer (FIT).
The processor detects a time-out when a 0 to 1 transition occurs on the time-base bit
corresponding to the fixed-interval time period.
When a time-out is detected, the processor sets the FIT-status bit in the timer-status register
(TSR[FIS]) to 1. At the beginning on the next clock cycle, the set TSR[FIS] bit causes the FIT
interrupt to occur.
This exception is persistent. To prevent repeated interrupts from occurring, the interrupt
handler must clear the exception status in TSR[FIS] before returning.
This interrupt is enabled only by setting both of the following:
• The FIT-interrupt enable bit in the timer-control register (TCR[FIE]) must be set to 1.
• The external-interrupt enable bit in the machine-state register (MSR[EE]) must be set
to 1.
If either TCR[FIE]
=
0 or MSR[EE]
=
0, a FIT interrupt does not occur. See Chapter 8, Timer
Resources , for more information on the FIT, TCR, and TSR.
Affected Registers
The timer-status register (TSR) is also updated as a result of a FIT exception.
Register Value After Interrupt
SRR0 Loaded with the effective address of the next-sequential instruction to be
executed at the point the interrupt occurs.
SRR1 Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2 Not used.
SRR3
ESR
DEAR
MSR [AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR]
←
0.
[CE, ME, DE]
←
Unchanged.
Register Value After Exception
TSR [FIS]
←
1.
All others are unchanged.