March 2002 Release
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
User Registers
R
Condition Register (CR)
The condition register (CR) is a 32-bit register that reflects the result of certain instructions
and provides a mechanism for testing and conditional branching. The bits in the CR are
grouped into eight 4-bit fields, CR0–CR7, as shown in
. The bits within an
arbitrary CR
n
. In this figure, the bit positions shown are
relative positions within the field rather than absolute positions within the CR register.
In the PPC405, the CR fields are modified in the following ways:
•
The
mtcrf
instruction can update specific fields in the CR from a GPR.
•
The
mcrxr
instruction can update a CR field with the contents of XER[0:3].
•
The
mcrf
instruction can copy one CR field into another CR field.
•
The condition-register logical instructions can update specific bits in the CR.
•
The integer-arithmetic instructions can update CR0 to reflect their result.
•
The integer-compare instructions can update a specific CR field to reflect their result.
Conditional-branch instructions can test bits in the CR and use the results of such a test as
the branch condition.
CR0 Field
The CR0 field is updated to reflect the result of an integer instruction if the Rc opcode field
(record bit) is set to 1. The
addic
.,
andi
., and
andis
. instructions also update CR0 to reflect
the result they produce. For all of these instructions, CR0 is updated as follows:
•
The instruction result is interpreted as a signed integer and algebraically compared to
0. The first three bits of CR0 (CR0[0:2]) are updated to reflect the result of the algebraic
comparison.
•
The fourth bit of CR0 (CR0[3]) is copied from XER[SO].
The CR0 bits are interpreted as described in
. If any portion of the result is
undefined, the value written into CR0[0:2] is undefined.
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
Figure 3-3:
Condition Register (CR)
0
1
2
3
LT
GT
EQ
SO
Figure 3-4:
CR
n
Field
