558
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
R
Figure 9-9:
JTAG-Connector Physical Layout
UG011_49_033101
15
1
16
2
0.1"
0.1"
Table 9-13:
JTAG Connector Signals
Pin
I/O
Signal Name
Description
1
O
TDO
JTAG test-data out.
2
NC
Reserved (no connection)
3
I
TDI
1
JTAG test-data in.
4
I
TRST
5
NC
Reserved (no connection)
6
I
+Power
2
Processor power OK
7
I
TCK
3
JTAG test clock.
8
NC
Reserved (no connection)
9
I
TMS
JTAG test-mode select.
10
NC
Reserved (no connection)
11
I
HALT
Processor halt.
12
NC
Reserved (no connection)
13
NC
Reserved (no connection)
14
KEY
No pin should be placed at this position.
15
NC
Reserved (no connection)
16
GND
Ground
Notes:
1.
A 10K
Ω
pull-up resistor should be connected to this signal to reduce chip-power consumption.
The pull-up resistor is not required.
2.
The +POWER signal, is provided by the board, and indicates whether the processor is
operating. This signal does not supply
power
to the debug tools or to the processor. A series
resistor (1K
Ω
or less) should be used to provide short-circuit current-limiting protection.
3.
A 10K
Ω
pull-up resistor must be connected to these signals to ensure proper chip operation
when these inputs are not used.
