336
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 1:
Introduction to the PPC405
R
The execute unit supports all 32-bit PowerPC UISA integer instructions in hardware, and is
compliant with the PowerPC embedded-environment architecture specification. Floating-
point operations are not supported.
The MAC unit supports implementation-specific multiply-accumulate instructions and
multiply-halfword instructions. MAC instructions operate on either signed or unsigned
16-bit operands, and they store their results in a 32-bit GPR. These instructions can
produce results using either modulo arithmetic or saturating arithmetic. All MAC
instructions have a single cycle throughput. See
Multiply-Accumulate Instruction-Set
for more information.
Exception Handling Logic
Exceptions are divided into two classes: critical and noncritical. The PPC405 CPU services
exceptions caused by error conditions, the internal timers, debug events, and the external
interrupt controller (EIC) interface. Across the two classes, a total of 19 possible exceptions
are supported, including the two provided by the EIC interface.
Each exception class has its own pair of save/restore registers. SRR0 and SRR1 are used for
noncritical interrupts, and SRR2 and SRR3 are used for critical interrupts. The exception-
return address and the machine state are written to these registers when an exception
occurs, and they are automatically restored when an interrupt handler exits using the
return-from-interrupt (
rfi
) or return-from critical-interrupt (
rfci
) instruction. Use of
separate save/restore registers allows the PPC405 to handle critical interrupts
independently of noncritical interrupts.
See
, for information on exception handling in the
PPC405.
Memory Management Unit
The PPC405 supports 4 GB of flat (non-segmented) address space. The memory-
management unit (MMU) provides address translation, protection functions, and storage-
attribute control for this address space. The MMU supports demand-paged virtual
memory using multiple page sizes of 1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB and
16 MB. Multiple page sizes can improve memory efficiency and minimize the number of
TLB misses. When supported by system software, the MMU provides the following
functions:
•
Translation of the 4 GB logical-address space into a physical-address space.
•
Independent enabling of instruction translation and protection from that of data
translation and protection.
•
Page-level access control using the translation mechanism.
•
Software control over the page-replacement strategy.
•
Additional protection control using zones.
•
Storage attributes for cache policy and speculative memory-access control.
The translation look-aside buffer (TLB) is used to control memory translation and
protection. Each one of its 64 entries specifies a page translation. It is fully associative, and
can simultaneously hold translations for any combination of page sizes. To prevent TLB
contention between data and instruction accesses, a 4-entry instruction and an 8-entry data
shadow-TLB are maintained by the processor transparently to software.
Software manages the initialization and replacement of TLB entries. The PPC405 includes
instructions for managing TLB entries by software running in privileged mode. This
capability gives significant control to system software over the implementation of a page
replacement strategy. For example, software can reduce the potential for TLB thrashing or
delays associated with TLB-entry replacement by reserving a subset of TLB entries for
globally accessible pages or critical pages.
Storage attributes are provided to control access of memory regions. When memory
translation is enabled, storage attributes are maintained on a page basis and read from the
