Xilinx Virtex-II Pro PPC405, User Manual

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Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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Debug Interface
The PPC405 provides a JTAG interface and trace interface to support testing
and debugging of both hardware and software. Typically, the JTAG interface is
exposed at the board level as a JTAG debug port, where an external debugger
can connect to it using a JTAG connector. The trace interface is also exposed at
the board level using a separate interface.
JTAG Debug Port
The PPC405 JTAG (Joint Test Action Group) debug port complies with IEEE
standard 1149.1–1990,
IEEE Standard Test Access Port and Boundary Scan
Architecture . This standard describes a method for accessing internal chip
resources using a four-signal or five-signal interface. The PPC405 JTAG debug
port supports scan-based board testing and is further enhanced to support the
attachment of debug tools. These enhancements comply with the IEEE 1149.1
specifications for vendor-specific extensions and are compatible with
standard JTAG hardware for boundary-scan system testing.
The PPC405 JTAG debug port supports the following;
• JTAG Signals —The JTAG debug port implements the four required JTAG
signals: TCK, TMS, TDI, and TDO. It also implements the optional TRST
signal.
• JTAG Clock —The frequency of the JTAG clock signal (TCK) can range
from 0 MHz (DC) to one-half of the processor clock frequency.
• JTAG Reset —The JTAG-debug port logic is reset at the same time the
system is reset, using the JTAG reset signal (TRST). When TRST is
asserted, the JTAG TAP controller returns to the test-logic reset state.
The JTAG debug port supports the required extest , idcode , sample/preload , and
bypass instructions. The optional highz and clamp instructions are also
supported. Invalid instructions behave as the bypass instruction.
Refer to the PPC405 Processor Block Manual for more information on the
JTAG debug-port signals. Information on JTAG is found in the IEEE standard
1149.1–1990.
JTAG Connector
A male, 16-pin 2x8-header connector is suggested for use as the JTAG debug
port connector. This connector supports direct attachment to the IBM
RISCWatch debugger. The layout of the connector is shown in
Figure 9-9 and
the signals are described in Table 9-13 . At the board level, the connector
should be placed as close as possible to the processor chip to ensure signal
integrity. Position 14 is used as a connection key and does not contain a pin.