March 2002 Release
759
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
twi
Trap Word Immediate
Description
The TO opcode field specifies the test conditions to be performed on the contents of
register
r
A and the sign-extended SIMM field (sign-extended to 32 bits). See
for more information on the TO field. If any test condition is met, a trap occurs as
follows:
•
If the trap-instruction debug event is not enabled (DBCR[TDE]
=
0, or both
DBCR[IDM]
=
0 and
DBCR[EDM]
=
0), a program interrupt occurs.
•
If the trap-instruction debug event is enabled as an external-debug event
(DBCR[TDE]
=
1 and DBCR[EDM]
=
1), the processor enters the debug stop state. An
external debugger is used to control the processor from this state.
Also, if internal-debug events are enabled (DBCR[IDM]
=
1) and debug exceptions are
disabled (MSR[DE]
=
0), an imprecise debug-event is reported by setting DBSR[IDE] to
1.
•
If the trap-instruction debug event is enabled as an internal-debug event
(DBCR[TDE]
=
1, DBCR[IDM]
=
1, and
DBCR[EDM]
=
0), the action taken depends on
whether debug exceptions are enabled:
-
If debug exceptions are enabled (MSR[DE]
=
1) a debug interrupt occurs.
-
If debug exceptions are disabled (MSR[DE]
=
0) a program interrupt occurs. An
imprecise debug-event is also reported by setting DBSR[IDE] to 1.
Refer to the following for more information:
•
•
.
•
.
•
.
•
Simplified mnemonics defined for this instruction are described in
Pseudocode
if
((
r
A)
EXTS(SIMM))
∧
(TO
0
=
1)
then trap
if
((
r
A)
EXTS(SIMM))
∧
(TO
1
=
1)
then trap
if
((
r
A)
EXTS(SIMM))
∧
(TO
2
=
1)
then trap
if
((
r
A)
EXTS(SIMM))
∧
(TO
3
=
1)
then trap
if
((
r
A)
EXTS(SIMM))
∧
(TO
4
=
1)
then trap
twi
TO,
r
A, SIMM
D Instruction Form
3
TO
rA
SIMM
0
6
1
1
1
6
3
1
<
>
=
<
u
>
u
