March 2002 Release
623
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
divw
Divide Word
Description
The contents of register
r
A (dividend) are divided by the contents of register
r
B (divisor).
The quotient is loaded into register
r
D. Both the dividend and the divisor are interpreted as
signed integers. The quotient is the unique signed integer that satisfies the equation:
dividend
=
(quotient
×
divisor) + remainder
where the remainder has the same sign as the dividend, and:
•
0
≤
remainder
<
divisor
, if the dividend is positive.
•
−
divisor
<
remainder
≤
0, if the dividend is negative.
The 32-bit remainder can be calculated using the following sequence of instructions:
divw
r
D,
r
A,
r
B
#
r
D
=
quotient
mullw
r
D,
r
D,
r
B
#
r
D
=
quotient
×
divisor
subf
r
D,
r
D,
r
A
#
r
D
=
remainder
The contents of register
r
D are undefined if an attempt is made to perform either of the
following invalid divisions:
•
0x8000 0000
÷
−
1.
•
n
÷
0, where
n
is any number.
The contents of CR[CR0]
LT, GT, EQ
are undefined if the Rc field is set to 1 and an invalid
division is performed. Both invalid divisions set XER[OV, SO] to 1 if the OE field contains
1.
Pseudocode
(
r
D)
←
(
r
A)
÷
(
r
B)
Registers Altered
•
r
D.
•
CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
•
XER[OV, SO] if OE
=
1.
Exceptions
•
None.
divw
r
D,
r
A,
r
B
(OE=0, Rc=0)
divw.
r
D,
r
A,
r
B
(OE=0, Rc=1)
divwo
r
D,
r
A,
r
B
(OE=1, Rc=0)
divwo.
r
D,
r
A,
r
B
(OE=1, Rc=1)
XO Instruction Form
31
r
D
r
A
r
B
OE
491
Rc
0
6
1
1
1
6
2
1
2
2
3
1
