Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 641
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
lbzx
Load Byte and Zero Indexed
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
The byte referenced by EA is extended to 32 bits by concatenating 24 0-bits on the left. The
result is loaded into register
r D.
Pseudocode
EA
←
( r A|0) + ( r B)
(
r D)
←
24
0 || MS(EA,1)
Registers Altered
• r D.
Exceptions
• Data storage—if the access is prevented by no-access-allowed zone protection. This
only applies to accesses in user mode when data relocation is enabled.
• Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
lbzx r D, r A, r B
X Instruction Form
31 r D r A r B 87 0
0 6 1
1 1
6 2
1 3
1