March 2002 Release
691
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
mulhw
Multiply High Word
Description
The contents of register
r
A are multiplied with the contents of register
r
B, forming a 64-bit
signed product. The most-significant 32 bits of the result are loaded into register
r
D.
mulhwu
should be used if the operands are to be interpreted as unsigned quantities.
This instruction can be used with
mullw
or
mulli
to calculate a full 64-bit product.
Pseudocode
prod
0:63
←
(
r
A)
×
(
r
B) signed
(
r
D)
←
prod
0:31
Registers Altered
•
r
D.
•
CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
Exceptions
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
mulhw
r
D,
r
A,
r
B
(Rc=0)
mulhw.
r
D,
r
A,
r
B
(Rc=1)
XO Instruction Form
31
r
D
r
A
r
B
0
75
Rc
0
6
1
1
1
6
2
1
2
2
3
1