Xilinx Virtex-II Pro PPC405, User Manual

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740 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
stwux
Store Word with Update Indexed
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• The contents of register r A are used as the base address.
The contents of register r S are stored into the word referenced by EA. The EA is loaded into
r A
.
Pseudocode
EA
←
(
r A) + ( r B)
MS(EA, 4)
←
( r S)
( r A)
←
EA
Registers Altered
• r A.
Exceptions
• Data storage—if the access is prevented by zone protection when data relocation is
enabled.
-
No-access-allowed zone protection applies only to accesses in user mode.
- Read-only zone protection applies to user and privileged modes.
• Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• Reserved bits containing a non-zero value.
• r A
=
0.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
stwux r S , r A, r B
X Instruction Form
31 r S r A r B 183 0
0 6 1
1 1
6 2
1 3
1