566
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
R
isync
;
/* Synchronize the context.
*/
/* ------------------------------------------------- */
/* Invalidate the data cache and enable cachability. */
/* ------------------------------------------------- */
address = 0;
/* Start with the first congruence class. */
/* Iterate through the data-cache congruence classes. */
for (line = 0; line <256; line++)
{
dccci(address);/* Invalidate the congruence class. */
a= 32; /* Point to the next congruence class. */
}
mtspr(DCWR, write-back, write-through); /* Set the caching
policy. */
mtspr(DCCR, d_cache_cachability);
/* Enable the data
cache. */
isync
;
/* Synchronize the
context. */
/* ---------------------------------- */
/* Prepare the system for interrupts. */
/* ---------------------------------- */
/* Load interrupt handlers. */
/* Initialize interrupt-vector table. */
/* Initialize exception-vector prefix */
mtspr(EVPR, prefix_addr);
/* ------------------------------------------- */
/* Prepare system for asynchronous interrupts. */
/* ------------------------------------------- */
/* Initialize and configure timer resources. */
mtspr(PIT, 0);
/* Disable PIT. */
mtspr(TSR, 0xFFFFFFFF);
/* Clear TSR */
mtspr(TCR, timer_enable);/* Enable desired timers */
mtspr(TBL, 0);
/* First clear TBL to avoid
rollover. */
mtspr(TBU, time_base_u); /* Set TBU to desired value. */
mtspr(TBL, time_base_l); /* Set TBL to desired value. */
mtspr(PIT, pit_count);
/* Initialize PIT. */
/* Enable exceptions immediately to avoid missing timer
events. */
mtmsr(enable_exceptions);
/* ------------------------------------------------------ */
/* The MSR also controls:
*/
/* 1. Privileged and user mode
*/
/* 2. Address translation
*/
/* These can be initialized by the operating system.
*/
/* ------------------------------------------------------ */
/* If enabling translation, the TLB must be initialized. */
/* Set the machine state as desired. */
mtmsr(machine_state);
