March 2002 Release
337
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
PPC405 Features
R
TLB when a memory access occurs. When memory translation is disabled, storage
attributes are maintained in storage-attribute control registers. A zone-protection register
(ZPR) is provided to allow system software to override the TLB access controls without
requiring the manipulation of individual TLB entries. For example, the ZPR can provide a
simple method for denying read access to certain application programs.
, describes these memory-management
resources in detail.
Instruction and Data Caches
The PPC405 accesses memory through the instruction-cache unit (ICU) and data-cache
unit (DCU). Each cache unit includes a PLB-master interface, cache arrays, and a cache
controller. Hits into the instruction cache and data cache appear to the CPU as single-cycle
memory accesses. Cache misses are handled as requests over the PLB bus to another PLB
device, such as an external-memory controller.
The PPC405 implements separate instruction-cache and data-cache arrays. Each is 16 KB in
size, is two-way set-associative, and operates using 8-word (32 byte) cachelines. The caches
are non-blocking, allowing the PPC405 to overlap instruction execution with reads over
the PLB (when cache misses occur).
The cache controllers replace cachelines according to a least-recently used (LRU)
replacement policy. When a cacheline fill occurs, the most-recently accessed line in the
cache set is retained and the other line is replaced. The cache controller updates the LRU
during a cacheline fill.
The ICU supplies up to two instructions every cycle to the fetch and decode unit. The ICU
can also forward instructions to the fetch and decode unit during a cacheline fill,
minimizing execution stalls caused by instruction-cache misses. When the ICU is accessed,
four instructions are read from the appropriate cacheline and placed temporarily in a line
buffer. Subsequent ICU accesses check this line buffer for the requested instruction prior to
accessing the cache array. This allows the ICU cache array to be accessed as little as once
every four instructions, significantly reducing ICU power consumption.
The DCU can independently process load/store operations and cache-control instructions.
The DCU can also dynamically reprioritize PLB requests to reduce the length of an
execution stall. For example, if the DCU is busy with a low-priority request and a
subsequent storage operation requested by the CPU is stalled, the DCU automatically
increases the priority of the current (low-priority) request. The current request is thus
finished sooner, allowing the DCU to process the stalled request sooner. The DCU can
forward data to the execute unit during a cacheline fill, further minimizing execution stalls
caused by data-cache misses.
Additional features allow programmers to tailor data-cache performance to a specific
application. The DCU can function in write-back or write-through mode, as determined by
the storage-control attributes. Loads and stores that do not allocate cachelines can also be
specified. Inhibiting certain cacheline fills can reduce potential pipeline stalls and
unwanted external-bus traffic.
See
, for details on the operation and control of
the PPC405 caches.
Timer Resources
The PPC405 contains a 64-bit time base and three timers. The time base is incremented
synchronously using the CPU clock or an external clock source. The three timers are
incremented synchronously with the time base. (See
, for more
information on these features.) The three timers supported by the PPC405 are:
•
Programmable Interval Timer
•
Fixed Interval Timer
•
Watchdog Timer
