Xilinx Virtex-II Pro PPC405, User Manual

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380 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
Register Indirect
Only load-string and store-string instructions can use this addressing mode. This mode
uses only the contents of the general-purpose register specified by the
r A operand as the
effective address. Rather than using the contents of r 0, a zero in the r A operand causes an
effective address of zero to be generated. The option to specify r A or 0 is shown in the
instruction descriptions as ( r A|0).
Figure 3-19 shows how an effective address is generated when using register-indirect
addressing.
Figure 3-18: Register-Indirect with Index Addressing
UG011_01_033101
Instruction Encoding
Opcode r D/ r S r A r B Subopcode 0
0 6 11 16 20 31
( r B)
0 31
Effective Address
0 31
+
( r A)
0 31
0000 0000 0000 0000 0000 0000 0000 0000
0 31
r A
=
0?
Yes
No
Figure 3-19: Register-Indirect Addressing
UG011_03_033101
Instruction Encoding
Opcode r D/ r S r A NB Subopcode 0
0 6 11 16 20 31
Effective Address
0 31
( r A)
0 31
0000 0000 0000 0000 0000 0000 0000 0000
0 31
r A
=
0?
Yes
No