Xilinx Virtex-II Pro PPC405, User Manual

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386 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
and storing data in big-endian order. For more information about big-endian and little-
endian byte ordering, see
Byte Ordering , page 349 .
Load and Store Multiple Instructions
Table 3-22 lists the PowerPC load and store multiple instructions and their operation.
Figure 3-21 shows how bytes are moved between memory and the GPRs for each of these
instructions.
These instructions are used to move blocks of data between memory and the GPRs. When
the
load multiple word instruction ( lmw ) is executed, r D through r 31 are loaded with n
Table 3-21: Load and Store with Byte-Reverse Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lhbrx Load Halfword Byte-Reverse Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r D, r A, r B
lwbrx Load Word Byte-Reverse Indexed
sthbrx Store Halfword Byte-Reverse Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r S, r A, r B
stwbrx Store Word Byte-Reverse Indexed
Figure 3-20: Load and Store with Byte-Reverse Instructions
UG011_04_091301
lhbrx
0 31 24 8 16
0 8 15
Byte 1 Byte 0
0000_0000 Byte 1 Byte 0 0000_0000
r D
Memory Halfword
0 31 24 8 16
0 31 24 8 16
Byte 1 Byte 2 Byte 3 Byte 0
Byte 2 Byte 1 Byte 0 Byte 3
r D
Memory Word
lwbrx
r S
0 31 24 8 16
0 8
Byte 2 Byte 3
Byte 1 Byte 2 Byte 3 Byte 0
Memory Halfword
15
sthbrx
r S
0 31 24 8 16
0 31 24 8 16
Byte 2 Byte 1 Byte 0 Byte 3
Byte 1 Byte 2 Byte 3 Byte 0
Memory Word
stwbrx
Big-Endian
Little-Endian