Xilinx Virtex-II Pro PPC405, User Manual

Page: 79 / 562

March 2002 Release www.xilinx.com 387
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Integer Load and Store Instructions
R
consecutive words from memory, where n =32- r D. For the lmw instruction, if r A is in the
range of registers to be loaded, or if r D=0, the instruction form is invalid. When the store
multiple word instruction ( stmw ) is executed, the n consecutive words in r S through r 31 are
stored into memory, where n =32- r S.
Load and Store String Instructions
Table 3-23 lists the PowerPC load and store string instructions and their addressing modes.
See the individual instruction listings in Chapter 11, Instruction Set for more information
on their operation and restrictions on the instruction forms.
Table 3-22: Load and Store Multiple Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lmw Load Multiple Word Register-indirect with immediate index
EA
=
( r A|0)
+
d
r D,d( r A)
stmw Store Multiple Word Register-indirect with immediate index
EA
=
( r A|0)
+
d
r S,d( r A)
Figure 3-21: Load and Store Multiple Instructions
UG011_05_033101
stmw
Word 0
Word n-1
. . .
Word 0
. . .
Word n-1
Memory GPRs
lmw
Word 0
Word n-1
. . .
Word 0
. . .
Word n-1
Memory GPRs
r D
r 31
. . .
r 0
. . .
r D
r 31
. . .
r 0
. . .
EA
EA + 4(n-1)
EA
EA + 4(n-1)