GPMC_FCLK
GPMC_CLK
nBE1/nBE0
nCS
nADV
nOE
DIR
WAIT
Valid Address
Valid Address
Data 0
Data 0
OUT
IN
OUT
WAITPINMONITORING = 0b01
WAITPINMONITORING = 0b00
CSONTIME
CSRDOFFTIME
ADVONTIME
ADVRDOFFTIME
OEONTIME
OEOFFTIME
RDACCESSTIME
RDCYCLETIME
A[27:17]
A[16:1]/D[15:0]
Preliminary
Architecture
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Figure 5-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1)
The WAIT signal is active low. GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME = 00b or 01b.
5.2.4.8.3.3 Wait Monitoring During an Asynchronous Write Access
When wait-pin monitoring is enabled for write accesses (GPMC_CONFIG1_i[21]
WAITWRITEMONITORING bit = 1), the WAIT-invalid timing window is defined by the
WRACCESSTIME field. WRACCESSTIME must be set so that the wait pin is at a valid state two
GPMC clock cycles before WRACCESSTIME completes. The advance pipelining of the two GPMC
clock cycles is the result of the internal synchronization requirements for the WAIT signal.
•
WAIT monitored as active freezes the CYCLETIME counter. This informs the GPMC that the data
bus is not captured by the external device. The control signals are kept in their current state. The
data bus still drives the data.
•
WAIT monitored as inactive unfreezes the CYCLETIME counter. This informs that the data bus is
correctly captured by the external device. All signals, including the data bus, are controlled
according to their related control timing value and to the CYCLETIME counter status.
566
General-Purpose Memory Controller (GPMC)
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated