Preliminary
Architecture
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5.2.4.12.4.2 Prefetch Mode
The prefetch mode is selected when the GPMC_PREFETCH_CONFIG1[0] ACCESSMODE bit is
cleared.
The MPU NAND software driver must issue the block and page opening (READ) command with the
correct data address pointer initialization before the engine can be started to read from the NAND
memory device. The engine is started by asserting the GPMC_PREFETCH_CONTROL[0]
STARTENGINE bit. The STARTENGINE bit automatically clears when the prefetch process completes.
If required, the ECC calculator engine must be initialized (i.e., reset, configured, and enabled) before
the prefetch engine is started, so that the ECC is correctly computed on all data read by the prefetch
engine.
When the GPMC_PREFETCH_CONFIG1[3] SYNCHROMODE bit is cleared, the prefetch engine starts
requesting data as soon as the STARTENGINE bit is set. If using this configuration, the host must
monitor the NAND device-ready pin so that it only sets the STARTENGINE bit when the NAND device
is in a ready state, meaning data is valid for prefetching.
When the SYNCHROMODE bit is set, the prefetch engine starts requesting data when an active to
inactive wait signal transition is detected. The transition detector must be cleared before any transition
detection; see
. The GPMC_PREFETCH_CONFIG1[5-4] WAITPINSELECTOR field
selects which gpmc_wait pin edge detector triggers the prefetch engine in this synchronized mode.
If the STARTENGINE bit is set after the NAND address phase (page opening command), the engine is
effectively started only after the actual NAND address phase completion. To prevent GPMC stall during
this NAND address phase, set the STARTENGINE bit field before NAND address phase completion
when in synchronized mode. The prefetch engine will start when an active to inactive wait signal
transition is detected. The STARTENGINE bit is automatically cleared on prefetch process completion.
The prefetch engine issues a read request to fill the FIFO with the amount of data specified by
GPMC_PREFETCH_CONFIG2[13-0] TRANSFERCOUNT field.
describes the prefetch mode configuration.
Table 5-22. Prefetch Mode Configuration
Bit Field
Register
Value
Comments
STARTENGINE
GPMC_PREFETCH_CONTROL
0
Prefetch engine can be configured only if
STARTENGINE is cleared to 0.
ENGINECSSELECTOR
GPMC_PREFETCH_CONFIG1
0 to 3h
Selects the chip-select associated with a
NAND device where the prefetch engine is
active.
ACCESSMODE
GPMC_PREFETCH_CONFIG1
0
Selects prefetch mode
FIFOTHRESHOLD
GPMC_PREFETCH_CONFIG1
Selects the maximum number of bytes read
or written by the host on DMA or interrupt
request
TRANSFERCOUNT
GPMC_PREFETCH_CONFIG1
Selects the number of bytes to be read or
written by the engine to the selected
chip-select
SYNCHROMODE
GPMC_PREFETCH_CONFIG1
0/1
Selects when the engine starts the access to
the chip-select
WAITPINSELECT
GPMC_PREFETCH_CONFIG1
0 to 1
Selects wait pin edge detector (if
GPMC_PREFETCH_CONFIG1[3]
SYNCHROMODE = 1)
ENABLEOPTIMIZEDACCESS
GPMC_PREFETCH_CONFIG1
0/1
See
CYCLEOPTIMIZATION
GPMC_PREFETCH_CONFIG1
Number of clock cycle removed to timing
parameters
ENABLEENGINE
GPMC_PREFETCH_CONFIG1
1
Engine enabled
STARTENGINE
GPMC_PREFETCH_CONFIG1
1
Starts the prefetch engine
628 General-Purpose Memory Controller (GPMC)
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated