Preliminary
www.ti.com
Architecture
Table 6-6. Clocks and Resets
Module
Destination Signal Name
Source Signal Name
Source
Destination
Instance
Clocks
The CEC/DDC clock is derived
from this clock. Also reference
DSS_HDMI
HDMI_PHY_48_S_FCLK
PRCM
clock for HDMI_TXPHY
module.
HDMI
HDMI_ICLK
DSS_L3_ICLK
PRCM
Interface clock
The TMDS encoded data is
TCLK
TMDS_CLK
HDMI_TXPHY
sent to the HDMI_TXPHY
module on this clock.
VPSS
VIDEO_S_PCLK
HDMI_CLK
VPSS
HDMI
Resets
HDMI
HDMI_RST
HDMI_IN_RST
PRCM
Nonretention reset
Table 6-7. Hardware Requests
Module
Desination Signal Name
Source Signal Name
Destination
Description
Instance
HDMI
DSS_HDMI_IRQ
intr0_intr_pend_n_38
CortexA8
HDMI Interrupt Request
HDMI
DSS_HDMI_DMA
EDMA_53
EDMA
HDMI audio DMA request
6.2.5 Power Management
describes the power-management features available to the HDMI module.
NOTE:
For information about source clock gating and a description of the sleep/wake-up
transitions, see the Sleep (Idle) and Wake-Up Management section in the Power, Reset,
and Clock Management..
For descriptions of the EnaWakeUp, IdleMode, ClockActivity, and StandbyMode features,
see the AutoIDLE Clock Control section in the Power, Reset, and Clock Management.
Table 6-8. Local Power-Management Features
Feature
Registers
Description
Slave idle modes
HDMI_WP_SYSCONFIG[3:2] IDLEMODE bit field
Force-idle, no-idle, smart-idle, and smart-idle
wakeup-capable modes are available.
705
SPRUGX9 – 15 April 2011
High-Definition Multimedia Interface (HDMI)
© 2011, Texas Instruments Incorporated