Preliminary
Chapter 1
SPRUGX9 – 15 April 2011
Chip Level Resources
Topic
...........................................................................................................................
Page
1.1
Introduction
......................................................................................................
1.2
MPU Subsystem
................................................................................................
1.3
C674x DSP Subsystem
.....................................................................................
1.4
System MMU
...................................................................................................
1.5
SGX530 Graphics Subsystem
............................................................................
1.6
HD Video Processing Subsystem (HDVPSS)
.......................................................
1.7
System Memory Map
........................................................................................
1.8
Device Interrupts
.............................................................................................
1.9
EDMA and EDMA Events
..................................................................................
1.10
Device Clocking and Flying Adder PLL
..............................................................
1.11
Bus Interconnect
.............................................................................................
1.12
Inter-Processor Communication
........................................................................
1.13
Mailbox
...........................................................................................................
1.14
Spinlock
.........................................................................................................
1.15
Error Location Module
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1.16
Control Module
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1.17
Interrupt Controller
..........................................................................................
1.18
Resets
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93
SPRUGX9 – 15 April 2011
Chip Level Resources
© 2011, Texas Instruments Incorporated