11
GPMC
gpmc_a[26:16]
Device
gpmc_d[15:0]
gpmc_ncs[7:0]
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nwp
gpmc_wait[1:0]
External device/
memory
A/D[15:0]
nADV
WAIT
nWE
nOE
nWP
nCE
A[26:16]
16
A[27:17]
nCS[7:0]
nADV/ALE
nOE/nRE
nWE
nBE0/CLE
nBE0/CLE
nBE1
nBE1
nWP
WAIT[1:0]
CLK
gpmc_clk
CLK
A[16:1]/D[15:0]
Preliminary
Architecture
www.ti.com
5.2.2 GPMC Modes
This section shows three GPMC external connections options:
•
shows a connection between the GPMC and a 16-bit synchronous
address/data-multiplexed (or AAD-multiplexed, but this protocol use less address pins) external
memory device.
•
shows a connection between the GPMC and a 16-bit synchronous nonmultiplexed
external memory device .
•
shows a connection between the GPMC and a 8-bit NAND device
Figure 5-2. GPMC to 16-Bit Address/Data-Multiplexed Memory
556
General-Purpose Memory Controller (GPMC)
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated