Preliminary
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List of Figures
1-1.
Microprocessor Unit (MPU) Subsystem
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1-2.
MicroProcessor Unit (MPU) Subsystem Signal Interface
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1-3.
MPU Subsystem Clocking Scheme
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1-4.
Reset Scheme of the MPU Subsystem
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1-5.
Overview of the AXI2OCP and the L3 Bridges
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1-6.
MPU Subsystem Power Domain Overview
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1-7.
TMS320C674x Megamodule Block Diagram
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1-8.
DSP Subsystem Block Diagram
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1-9.
TMS320C674x Megamodule Block Diagram
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1-10.
DSP Megamodule INTC Block Diagram
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1-11.
Typical MMU Intergration
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1-12.
MMU Block Diagram
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1-13.
MMU Address Translation Process
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1-14.
Translation Hierarchy
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1-15.
First-Level Descriptor Address Calculation
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1-16.
Detailed First-Level Descriptor Address Calculation
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1-17.
Section Translation Summary
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1-18.
Supersection Translation Summary
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1-19.
Two-Level Translation
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1-20.
Small Page Translation Summary
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1-21.
Large Page Translation Summary
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1-22.
TLB-Entry Lock Mechanism
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1-23.
TLB-Entry Structure
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1-24.
MMU Global Initialization
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1-25.
MMU_REVISION
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1-26.
MMU_SYSCONFIG
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1-27.
MMU_SYSSTATUS
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1-28.
MMU_IRQSTATUS
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1-29.
MMU_IRQENABLE
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1-30.
MMU_WALKING_ST
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1-31.
MMU_CNTL
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1-32.
MMU_FAULT_AD
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1-33.
MMU_TTB
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1-34.
MMU_LOCK
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1-35.
MMU_LD_TLB
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1-36.
MMU_CAM
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1-37.
MMU_RAM
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1-38.
MMU_GFLUSH
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1-39.
MMU_FLUSH_ENTRY
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1-40.
MMU_READ_CAM
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1-41.
MMU_READ_RAM
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1-42.
MMU_EMU_FAULT_AD
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1-43.
MMU_FAULT_PC
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1-44.
Graphics Accelerator Highlight
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1-45.
SGX Subsystem Integration
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1-46.
SGX Block Diagram
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1-47.
OCP Revision Register (OCP_REVISION)
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22
List of Figures
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated