TX FIFO Max
Level
Progammable
Threshold
(TXTRSH)
Zero Byte
TXTRSH
XRDY Condition
(Active Low)
Time
Time
Preliminary
Architecture
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In receive mode, RRDY interrupt is not generated until the FIFO reaches its receive threshold. Once
low, the interrupt can only be de-asserted when the Local Host has handled enough bytes to make the
FIFO level below threshold. For each interrupt, the Local Host can be configured to read an amount of
bytes equal with the value of the RX FIFO thr 1.
Figure 7-10. Transmit FIFO Interrupt Request Generation
Note that in the figure above, the XRDY Condition illustrates that the condition for generating a XRDY
interrupt is achieved. The interrupt request is generated when this condition is achieved (when TX FIFO
is empty, or the TX FIFO threshold is not reached and there are still data bytes to be transferred in the
TX FIFO), and it can be cleared only by the CPU by writing a 1 in the corresponding interrupt flag after
transmitting the configured number of bytes. If the condition is still present after clearing the previous
interrupt, another interrupt request will be generated.
Note that in interrupt mode, the module offers two options for the CPU application to handle the
interrupts:
•
When detecting an interrupt request (XRDY or RRDY type), the CPU can write/read one data byte
to/from the FIFO and then clear the interrupt. The module will not reassert the interrupt until the
interrupt condition is not met.
•
When detecting an interrupt request (XRDY or RRDY type), the CPU can be programmed to
write/read the amount of data bytes specified by the corresponding FIFO threshold
(I2C_BUF. 1 or I2C_BUF. 1). In this case, the interrupt condition will be
cleared and the next interrupt will be asserted again when the XRDY or RRDY condition will be
again met.
If the second interrupt serving approach is used, an additional mechanism (draining feature) is
implemented for the case when the transfer length is not a multiple of FIFO threshold (see the Draining
Feature subsection).
In slave TX mode, the draining feature cannot be used, since the transfer length is not known at the
configuration time, and the external master can end the transfer at any point by not acknowledging one
data byte.
7.2.13.2 FIFO Polling Mode Operation
In FIFO polled mode (I2C_IRQENABLE_SET.XRDY_IE and I2C_IRQENABLE_SET.RRDY_IE disabled
and DMA disabled), the status of the module (receiver or transmitter) can be checked by polling the
XRDY and RRDY status registers (I2C_IRQSTATUS_RAW) (RDR and XDR can also be polled if
draining feature must be used). The XRDY and RRDY flags are accurately reflecting the interrupt
conditions mentioned in Interrupt Mode. This mode is an alternative to the FIFO interrupt mode of
operation, where the status of the receiver and transmitter is automatically known by means of
interrupts sent to the CPU.
854
Inter-Integrated Circuit (I2C) Controller Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated