Preliminary
Memory Booting
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Table 21-13. Supported NAND Devices (continued)
Capacity
Device ID
Bus Width
Page size
2 Gb
AA
x8
2048
2 Gb
BA
x16
2048
2 Gb
83
x8
2048
2 Gb
93
x16
2048
4 Gb
DC
x8
2048
4 Gb
CC
x16
2048
4 Gb
AC
x8
2048/4096
4 Gb
BC
x16
2048/4096
4 Gb
84
x8
2048
4 Gb
94
x16
2048
8 Gb
D3
x8
2048/4096
8 Gb
C3
x16
2048/4096
8 Gb
A3
x8
2048/4096
8 Gb
B3
x16
2048/4096
8 Gb
85
x8
2048
8 Gb
95
x16
2048
16 Gb
D5
x8
2048/4096
16 Gb
C5
x16
2048/4096
16 Gb
A5
x8
2048/4096
16 Gb
B5
x16
2048/4096
16 Gb
86
x8
2048
16 Gb
96
x16
2048
32 Gb
D7
x8
2048/4096
32 Gb
C7
x16
2048/4096
32 Gb
A7
x8
2048/4096
32 Gb
B7
x16
2048/4096
32 Gb
87
x8
2048
32 Gb
97
x16
2048
64 Gb
DE
x8
2048/4096
64 Gb
CE
x16
2048/4096
64 Gb
AE
x8
2048/4096
64 Gb
BE
x16
2048/4096
When the parameters are retrieved from the ROM table: page size and block size is updated based on
4th byte of NAND ID data. Due to inconsistency amongst different manufacturers, only devices which
has been recognized to be at least 2Gb (included) have these parameters updated. Therefore, the
ROM Code supports 4kB page devices but only if their size, according to the table, is at least 2Gb.
Devices which are smaller than 2Gb have the block size parameter set to 128kB (when page size is
2KB).
shows the 4th ID Data byte encoding used in ROM Code.
Table 21-14. 4th NAND ID Data Byte
I/O #
Item
Description
7
6
5
4
3
2
1
0
Page Size
1kB
0
0
2kB
0
1
4kB
1
0
8kB
1
1
2006ROM Code Memory and Peripheral Booting
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated