Preliminary
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Control Module
1.16.1.2.28 Video PLL Frequency 2 Register (VIDEOPLL_FREQ2)
The VIDEOPLL_FREQ2 register is used to control the Video PLL Clock 2 pre-divider frequency of the
SYSCLK13 (HD_VENC_D clock) and STC0/STC1 source clocks. If the Video PLL Clock 2 is locked to a
transport stream System Time Clock (STC), the FREQ2 value will be modified by software to push or pull
the clock frequency as part of the clock recovery process. The default FREQ2 value is 10.0 to generate a
74.25 MHz SYSCLK13.
The Video PLL Frequency 2 Register (VIDEOPLL_FREQ2) is shown in
and described in
.
Figure 1-143. Video PLL Frequency 2 Register (VIDEOPLL_FREQ2)
31
30
29
28
27
24 23
0
VID_LDFREQ2
Reserved
VID_TRUNC2
VID_INTFREQ2
VID_FRACFREQ2
R/W-1
R-0
R/W-0
R/W-Ah
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-183. Video PLL Frequency 2 Register (VIDEOPLL_FREQ2) Field Descriptions
Bit
Field
Value
Description
31
VID_LDFREQ2
1-0
Load Synth2 FREQ value. Setting this bit to 1 causes the INTFREQ and
FRACFREQ values to be loaded into VIDEO Synthesizer2.
30-29
Reserved
0
Reserved. Read returns 0.
28
VID_TRUNC2
1-0
Synth2 Enable Truncate Correction.
27-24
VID_INTFREQ2
0-Fh
Synt25 Frequency integer divider.
23-0
VID_FRACFREQ2
0-FF FFFFh
Synth2 Frequency fractional divider.
1.16.1.2.29 Video PLL Divider 2 Register (VIDEOPLL_DIV2)
The VIDEOPLL_DIV2 register is used to control the VIDEO PLL Clock 2 post-divider frequency of the
SYSCLK13 and STC0/STC1 source clocks. The default DIV2 value is 2 to generate a 74.25 MHz.
The Video PLL Divider 2 Register (VIDEOPLL_DIV2) is shown in
and described in
.
Figure 1-144. Video PLL Divider 2 Register (VIDEOPLL_DIV2)
31
9
8
7
0
Reserved
VID_LDMDIV2
VID_MDIV2
R-0
R/W-1
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-184. Video PLL Divider 2 Register (VIDEOPLL_DIV2) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved. Read returns 0.¼
8
VID_LDMDIV2
1-0
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded
into VIDEO Synthesizer2.
7-0
VID_MDIV2
0-FFh
Synth2 Frequency M Post Divider.
291
SPRUGX9 – 15 April 2011
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