Texas Instruments TMS320C6A816 Series, Technical Reference Manual

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Data Sampling
clk
cmd, dat[x:0]
(Host
Card)
®
cmd, dat[x:0]
(Host
Card)
¬
tMOS tMOH
Valid OUT
tMIS
tCP
tC2
tC1
tMiH
Valid IN
Data Sampling
clk
cmd, dat[x:0]
(Host Card)
®
cmd, dat[x:0]
(Host Card)
¬
tMOS
tMOH
Valid OUT
tMIS
tCP
tC2
tC1
tMiH
Valid IN
Preliminary
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Architecture
9.2.11 Output Signals Generation
The SD/SDIO output signals can be driven on either falling edge or rising edge depending on the
SD_HCTL[2] HSPE bit. This feature allows to reach better timing performance, and thus to increase
data transfer frequency.
9.2.11.1 Generation on Falling Edge of Clock
The controller is by default in this mode to maximize hold timings. In this case, SD_HCTL[2] HSPE bit is
cleared to 0.
Figure 9-21 shows the output signals of the module when generating from the falling edge of the clock.
Figure 9-21. Output Driven on Falling Edge
9.2.11.2 Generation on Rising Edge of Clock
This mode increases setup timings and allows reaching higher bus frequency. This feature is activated
by setting SD_HCTL[2] HSPE bit to 1. The controller shall be set in this mode to support SDR transfers.
NOTE: Do not use this feature in Dual Data Rate mode (when SD_CON[19] DDR is set to 1).
Figure 9-22 shows the output signals of the module when generating from the rising edge of the clock.
Figure 9-22. Output Driven on Rising Edge
953 SPRUGX9 – 15 April 2011 Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
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