D[15:0]
WAIT
Data
OEOFFTIME
RDCYCLETIME
OEONTIME = 0
CSRDOFFTIME = RDCYCLETIME
CSONTIME = 0
RDACCESSTIME
nBE0/CLE
nCS
nOE/nRE
nADV/ALE
Preliminary
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Architecture
5.2.4.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
NAND device data read and write accesses are achieved through a read or write request to the
chip-select-associated memory region at any address location in the region or through a read or write
request to the GPMC_NAND_DATA_i location (i = 0 to 7) mapped in the chip-select-associated control
register region. GPMC_NAND_DATA_i is not a true register, but an address location to enable RE or
WE signal control. The associated chip-select signal timing control must be programmed according to
the NAND device timing specification.
Reading data from the GPMC_NAND_DATA_i location or from any location in the associated
chip-select memory region activates an asynchronous read access.
•
CS is controlled by the CSONTIME and CSRDOFFTIME timing parameters.
•
RE is controlled by the OEONTIME and OEOFFTIME timing parameters.
•
To take advantage of RE high-to-data invalid minimum timing value, the RDACCESSTIME can be
set so that data are effectively captured after RE deassertion. This allows optimization of NAND
read access cycle time completion. For optimal timing parameter settings, see the NAND device and
the device IC timing parameters.
ALE, CLE, and WE are maintained inactive.
shows the NAND data read cycle.
Figure 5-29. NAND Data Read Cycle
Writing data to the GPMC_NAND_DATA_i location or to any location in the associated chip-select
memory region activates an asynchronous write access.
•
CS is controlled by the CSONTIME and CSWROFFTIME timing parameters.
•
WE is controlled by the WEONTIME and WEOFFTIME timing parameters.
•
ALE, CLE, and RE (OE) are maintained inactive.
shows the NAND data write cycle.
605
SPRUGX9 – 15 April 2011
General-Purpose Memory Controller (GPMC)
© 2011, Texas Instruments Incorporated