Preliminary
Control Module
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1.16.1.2.26 Video PLL Frequency 1 Register (VIDEOPLL_FREQ1)
The VIDEOPLL_FREQ1 register is used to control the Video PLL Clock 1 pre-divider frequency of
SYSCLK17 (SD_VENC) and STC1 source clocks. The default FREQ1 value is 11.
Video PLL Frequency 1 Register (VIDEOPLL_FREQ1) is shown in
and described in
.
Figure 1-141. Video PLL Frequency 1 Register (VIDEOPLL_FREQ1)
31
30
29
28
27
24 23
0
VID_LDFREQ1
Reserved
VID_TRUNC1
VID_INTFREQ1
VID_FRACFREQ1
R/W-1
R-0
R/W-0
R/W-Bh
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-181. Video PLL Frequency 1 Register (VIDEOPLL_FREQ1) Field Descriptions
Bit
Field
Value
Description
31
VID_LDFREQ1
1-0
Load Synth1 FREQ value Setting this bit to 1 causes the INTFREQ and
FRACFREQ values to be loaded into VIDEO Synthesizer1.
30-29
Reserved
0
Reserved. Read returns 0.
28
VID_TRUNC1
1-0
Synth1 Enable Truncate Correction.
27-24
VID_INTFREQ1
0-Fh
Synth1 Frequency integer divider.
23-0
VID_FRACFREQ1
0-FF FFFFh
Synth1 Frequency fractional divider.
1.16.1.2.27 Video PLL Divider 1 Register (VIDEOPLL_DIV1)
The VIDEOPLL_DIV1 register is used to control the VIDEO PLL Clock 1 post-divider frequency of the
SYSCLK17 and STC0 source clocks. The default DIV1 value is 5.
The Video PLL Divider 1 Register (VIDEOPLL_DIV1) is shown in
and described in
.
Figure 1-142. Video PLL Divider 1 Register (VIDEOPLL_DIV1)
31
9
8
7
0
Reserved
VID_LDMDIV1
VID_MDIV1
R-0
R/W-1
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-182. Video PLL Divider 1 Register (VIDEOPLL_DIV1) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved. Read returns 0.
8
VID_LDMDIV1
1-0
Load Synth1 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded
into VIDEO Synthesizer1.
7-0
VID_MDIV1
0-FFh
Synth1 Frequency M Post Divider.
290
Chip Level Resources
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated