Preliminary
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Use Cases And Tips
5.4.1.3
GPMC Configuration for Synchronous Burst Read Access
The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
shows how to calculate timings for the GPMC using the memory parameters.
shows the synchronous burst read access.
Table 5-46. Useful Timing Parameters on the Memory Side
AC Read Characteristics
Description
Duration (ns)
on the Memory Side
tCES
CS setup time to clock
0
tACS
Address setup time to clock
3
tIACC
Synchronous access time
80
tBACC
Burst access time valid clock to output delay
5,2
tCEZ
Chip-select to High-Impedance
7
tOEZ
Output enable to High-Impedance
7
tAVC
ADV setup time
6
tAVD
AVD pulse
6
tACH
Address hold time from clock
3
The following terms, which describe the timing interface between the controller and its attached device,
are used to calculate the timing parameters on the GPMC side:
•
Read Access time (GPMC side): Time required to activate the clock + read access time requested
on the memory side + data setup time required for optimal capture of a burst of data
•
Data setup time (GPMC side): Ensures a good capture of a burst of data (as opposed to taking a
burst of data out). One word of data is processed in one clock cycle (T = 9,615 ns). The read
access time between 2 bursts of data is tBACC = 5,2 ns. Therefore, data setup time is a clock
period - tBACC = 4,415 ns of data setup.
•
Access completion (GPMC side): (Different from page burst access time) Time required between the
last burst access and access completion: CS/OE hold time (CS and OE must be released at the end
of an access. These signals are held to allow the access to complete).
•
Read cycle time (GPMC side): Read Access time + access completion
•
Write cycle time for burst access: Not supported for NOR flash memory
653
SPRUGX9 – 15 April 2011
General-Purpose Memory Controller (GPMC)
© 2011, Texas Instruments Incorporated