Preliminary
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Registers
6.3.2.85 Interrupt Unmask Register (INT_UNMASK2)
The interrupt unmask register is shown in
and described in
Figure 6-107. Interrupt Unmask Register (INT_UNMASK2)
31
16
Reserved
R-0h
15
8
Reserved
R-0h
7
6
5
4
3
2
1
0
BCAP_DONE
SPDIF_PAR
ENC_DIS
PREAM_ERR
CTS_CHG
ACR_OVR
TCLK_STBL
VSYNC_REC
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-116. Interrupt Unmask Register (INT_UNMASK2) Field Descriptions
Bit
Field
Description
31-8
Reserved
Reserved
7
BCAP_DONE
If set this interrupt detected that the FIFORDY bit is set to 1.
6
SPDIF_PAR
S/PDIF parity error. The S/PDIF stream includes a parity (P) bit at the end of each sub-frame. An interrupt
occurs if the calculated parity does not match the state of this bit.
5
ENC_DIS
The ENC_EN bit (in register HDCP_CTRL) changed from 1 to 0. This interrupt occurs if encryption is
turned off.
4
PREAM_ERR
This condition is the opposite of the condition that causes DROP_SAMPLE (in register INTR1). This
interrupt occurs if a preamble is expected but not found when decoding the S/PDIF stream.
3
CTS_CHG
Change in ACR CTS value. This interrupt occurs when the change is of an unexpected magnitude. Such
an interrupt should be expected when changing Fs or pixel clock frequency.
2
ACR_OVR
ACR packet overwrite. This interrupt occurs if the HDMI transmitter puts a NCTS packet into the queue
before the previous NCTS packet has been sent. This can happen if very long active data times do not
allow for sufficient NCTS packet bandwidth. For all CEA- 861D modes, no ACR_OVR interrupt should
occur.
1
TCLK_STBL
TCLK_STABLE. Whenever IDCK changes, there is a temporary instability in the internal clocking. This
interrupt is set when the internal clocking has stabilized.
0
VSYNC_REC
Asserted when VSYNC active edge is recognized, it is useful for triggering firmware actions that occur
during vertical blanking.
6.3.2.86 Interrupt Unmask Register (INT_UNMASK3)
The interrupt unmask register is shown in
and described in
Figure 6-108. Interrupt Unmask Register (INT_UNMASK3)
31
16
Reserved
R-0h
15
8
Reserved
R-0h
7
6
5
4
3
2
1
0
DDC_CMD_
DDC_FIFO_
DDC_FIFO_
DDC_FIFO_
RI_ERR_3
RI_ERR_2
RI_ERR_1
RI_ERR_0
DONE
HALF
FULL
EMPTY
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
787
SPRUGX9 – 15 April 2011
High-Definition Multimedia Interface (HDMI)
© 2011, Texas Instruments Incorporated