Preliminary
Registers
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3.3.3.8
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in
and described in
Figure 3-83. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
16
Reserved
R-0
15
2
1
0
Reserved
USERINTMASKED
R-0
R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 3-83. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved.
1-0
USERINTMASKED
0-3h
Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1.
USERINTMASKED[0] and USERINTMASKED[1] correspond to USERACCESS0 and
USERACCESS1, respectively. Writing a 1 will clear the interrupt and writing a 0 has no effect.
0
No MDIO user command complete event.
1
The previously scheduled PHY read or write command using MDIO user access register n
(USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1.
520
EMAC/MDIO Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated