C S0
OE
W E
t , t
wr
rd
, t
CEoff
t
, t
OEon
WEon
t
rddata
t
, t
OEoff
WEoff
Preliminary
Memory Booting
www.ti.com
21.7.3 NAND
The NAND flash memory is not XIP and requires shadowing before the code can be executed. The
features include:
•
GPMC as the communication interface
•
Device from 512Mbit (64 MByte)
•
×8 and ×16 bus width
•
Support for large page size (2048 bytes + 64 spare bytes) or very large page size 4096 bytes + 128
/ 218 spare bytes)
•
CE don’t care devices only
•
Single Level Cell (SLC) and Multiple Level Cell (MLC) devices
•
Device Identification based on ONFI or ROM table
•
ECC correction : 8 bits/sector for most devices (16b/sector for devices with large spare area)
•
GPMC timings adjusted for NAND access
•
55 MHz GPMC clock
•
Device connected to CS0
•
Wait pin signal WAITPIN0 connected to NAND BUSY output
•
Four physical blocks are searched for an image. The block size depends on device.
The initialization routine for NAND devices consists in three parts: GPMC initialization, device detection
with parameters determination and finally bad block detection.
•
ONFI support. The NAND identification starts with ONFI detection.
•
GPMC initialization. The GPMC interface is configured as such it can be used for accessing NAND
devices. The address bus is released since a NAND device does not use it. The data bus width is
initially set to 8 bits; and changed to 16 bits if needed after device parameters determination. The
following scheme is applied since NAND devices require different timings when compared to regular
NOR devices:
and
describes the timings configured for NAND device access. The one clock
cycle is 18.181 ns which correspond to 55 MHz frequency.
Figure 21-11. GPMC NAND Timings
2004
ROM Code Memory and Peripheral Booting
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated