Texas Instruments TMS320C6A816 Series Technical Reference Manual Download Page 947

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cmd

dat0

Command

Response

Host to

card

Card to

host

dat[3:1]

Command

Response

Card to

host

Host to

card

Busy

XXXX

cmd

dat0

Command

Response

Host to

card

Card to

host

Host to

card

Block write operation

dat[3:1]

Card to

host

Data block

+ CRC

Busy

CRC
Status

Data block

+ CRC

XXXX

Command

Response

Card to

host

Host to

card

Preliminary

www.ti.com

Architecture

9.2.8.1

Busy Timeout for R1b, R5b Response Type

Figure 9-13

shows DCRD event condition asserted when there is a busy timeout for R1b or R5b

responses.

Figure 9-13. Busy Timeout for R1b, R5b Responses

t1 - Data timeout counter is loaded and starts after R1b, R5b response type.

t2 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.

9.2.8.2

Busy Timeout After Write CRC Status

Figure 9-14

shows DCRC event condition asserted when there is busy timeout after write CRC status.

Figure 9-14. Busy Timeout After Write CRC Status

t1 - Data timeout counter is loaded and starts after CRC status.

t2 - Data timeout counter stops and if it is 0, SD_STAT[21] DCRC is generated.

947

SPRUGX9 – 15 April 2011

Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface

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Summary of Contents for TMS320C6A816 Series

Page 1: ...Preliminary TMS320C6A816x C6 Integra DSP ARM Processors Technical Reference Manual Literature Number SPRUGX9 15 April 2011...

Page 2: ...Preliminary 2 SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 3: ...2 MMU Intergration 117 1 4 3 MMU Functional Description 118 1 4 4 MMU Low level Programming Models 130 1 4 5 MMU Registers 133 1 5 SGX530 Graphics Subsystem 145 1 5 1 SGX Overview 145 1 5 2 SGX Integ...

Page 4: ...ontrol Module 270 1 16 1 Registers 270 1 17 Interrupt Controller 329 1 18 Resets 330 2 DMM TILER 331 2 1 Introduction 332 2 1 1 Overview 332 2 1 2 Features 333 2 1 3 Functional Block Diagram 333 2 1 4...

Page 5: ...AT 404 3 EMAC MDIO Module 405 3 1 Introduction 406 3 1 1 Overview 406 3 1 2 Features 406 3 1 3 Functional Block Diagram 407 3 1 4 EMAC and MDIO Block Diagram 407 3 1 5 Industry Standard s Compliance S...

Page 6: ...r 549 4 3 20 GPIO_SETDATAOUT Register 549 5 General Purpose Memory Controller GPMC 551 5 1 Introduction 552 5 1 1 Overview 552 5 1 2 Block Diagram 552 5 2 Architecture 554 5 2 1 GPMC Signals 554 5 2 2...

Page 7: ...GPMC_BCH_RESULT6_i 695 6 High Definition Multimedia Interface HDMI 697 6 1 Introduction 698 6 1 1 Overview 698 6 1 2 Main Features 698 6 1 3 Functional Block Diagram 699 6 1 4 Video Formats and Timin...

Page 8: ...keup Enable Register I2C_WE 873 7 3 10 Receive DMA Enable Set Register I2C_DMARXENABLE_SET 876 7 3 11 Transmit DMA Enable Set Register I2C_DMATXENABLE_SET 876 7 3 12 Receive DMA Enable Clear Register...

Page 9: ...OL Register 920 8 4 7 INTCPS_PROTECTION Register 921 8 4 8 INTCPS_IDLE Register 921 8 4 9 INTCPS_IRQ_PRIORITY Register 922 8 4 10 INTCPS_FIQ_PRIORITY Register 922 8 4 11 INTCPS_THRESHOLD Register 923...

Page 10: ...31 0 Register SD_RSP10 979 9 4 15 Command Response 63 32 Register SD_RSP32 979 9 4 16 Command Response 95 64 Register SD_RSP54 980 9 4 17 Command Response 127 96 Register SD_RSP76 980 9 4 18 Data Reg...

Page 11: ...ntrol Register AFSRCTL 1093 10 3 16 Receive Clock Control Register ACLKRCTL 1094 10 3 17 Receive High Frequency Clock Control Register AHCLKRCTL 1095 10 3 18 Receive TDM Time Slot Register RTDM 1096 1...

Page 12: ...smit Control Register 1 XCR1_REG 1184 11 3 9 McBSP Sample Rate Generator Register 2 SRGR2_REG 1185 11 3 10 McBSP Sample Rate Generator Register 1 SRGR1_REG 1186 11 3 11 McBSP Multichannel Register 2 M...

Page 13: ...ransmission 1215 12 2 3 Master Mode 1222 12 2 4 Slave Mode 1240 12 2 5 Interrupts 1244 12 2 6 DMA Requests 1245 12 2 7 Emulation Mode 1246 12 2 8 Power Saving Management 1247 12 2 9 System Test Mode 1...

Page 14: ...ion Type 1 Registers 1355 13 4 8 PCIe Capability Registers 1363 13 4 9 PCIe Extended Capability Registers 1373 13 4 10 Message Signaled Interrupts Registers 1382 13 4 11 Power Management Capability Re...

Page 15: ...TIVE Device 1468 14 7 9 PRM_DEFAULT Device 1471 14 7 10 PRM_SGX Device 1475 14 7 11 CM_ALWON Device 1477 15 Real Time Clock RTC 1535 15 1 Introduction 1536 15 1 1 Overview 1536 15 1 2 Features 1536 15...

Page 16: ...this Document 1567 16 2 Architecture 1568 16 2 1 Clock Control 1568 16 2 2 Signal Description 1569 16 2 3 DMA 1569 16 2 4 Transport Layer 1570 16 2 5 FIFOs 1570 16 2 6 Link Layer 1570 16 2 7 PHY 1570...

Page 17: ...rt Serial ATA Notification Register P SNTF 0 or 1 1623 16 4 33 Port DMA Control Register P DMACR 0 or 1 1624 16 4 34 Port PHY Control Register P PHYCR 0 or 1 1626 16 4 35 Port PHY Status Register P PH...

Page 18: ...upt Generation 1665 18 2 12 Watchdog Timers Under Emulation 1666 18 2 13 Accessing Watchdog Timer Registers 1666 18 3 Low Level Programming Model 1667 18 3 1 Global Initialization 1667 18 3 2 Operatio...

Page 19: ...728 19 3 17 Scratchpad Register SPR 1728 19 3 18 Trigger Level Register TLR 1729 19 3 19 Mode Definition Register 1 MDR1 1730 19 3 20 Mode Definition Register 2 MDR2 1731 19 3 21 Status FIFO Line Stat...

Page 20: ...Host and Peripheral Modes Operation 1759 20 3 Protocol Description s 1760 20 3 1 USB Controller Peripheral Mode Operation 1760 20 3 2 USB Controller Host Mode Operation 1777 20 4 Communications Port...

Page 21: ...e Start up 1994 21 4 2 CPU State at Public Startup 1995 21 4 3 Clocking Configuration 1995 21 5 Booting 1996 21 5 1 Overview 1996 21 5 2 Device List 1997 21 6 Fast Internal Booting 1999 21 6 1 Overvie...

Page 22: ...ion Translation Summary 122 1 18 Supersection Translation Summary 123 1 19 Two Level Translation 124 1 20 Small Page Translation Summary 125 1 21 Large Page Translation Summary 126 1 22 TLB Entry Lock...

Page 23: ...67 Detailed Clock Architecture 185 1 68 Flying Adder PLL 187 1 69 Main PLL Structure 188 1 70 DDR PLL Structure 191 1 71 Video PLL Structure 193 1 72 Audio PLL Structure 195 1 73 Clocks 198 1 74 L3 I...

Page 24: ...EQ2 278 1 121 Main PLL Divider 2 Register MAINPLL_DIV2 278 1 122 Main PLL Frequency 4 Register MAINPLL_FREQ4 279 1 123 Main PLL Divider 4 Register MAINPLL_DIV4 279 1 124 Main PLL Frequency 5 Register...

Page 25: ...MAC ID1 Low Register MAC_ID1_LO 311 1 170 Ethernet MAC ID1 High Register MAC_ID1_HI 311 1 171 PCIE Configuration Register PCIE_CFG 312 1 172 Clock Control Register CLK_CTL 313 1 173 Audio Interface C...

Page 26: ...ing in 90 or 270 Orientations S 1 360 2 31 Tiled Mode Ordering of Elements in Natural View 362 2 32 Page Mode Ordering of Elements in Natural View 362 2 33 Tiled Mode Ordering of Elements in 0 View wi...

Page 27: ...lock Diagram 407 3 2 Ethernet Configuration GMII Connections 411 3 3 Ethernet Frame Format 413 3 4 Basic Descriptor Format 414 3 5 Typical Descriptor Linked List 415 3 6 Transmit Buffer Descriptor For...

Page 28: ...ATMASKED 481 3 44 MAC Interrupt Mask Set Register MACINTMASKSET 482 3 45 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 482 3 46 Receive Multicast Broadcast Promiscuous Channel Enable Register RXMB...

Page 29: ...RACCESS1 525 3 89 MDIO User PHY Select Register 1 USERPHYSEL1 526 4 1 GPIO Block Diagram 529 4 2 Synchronous Path Block Diagram 529 4 3 Interrupt Request Generation 532 4 4 Write GPIO_CLEARDATAOUT Reg...

Page 30: ...ata Multiplexed Mode 594 5 24 Asynchronous Single Read on an Address Data Nonmultiplexed Device 596 5 25 Asynchronous Single Write on an Address Data Nonmultiplexed Device 597 5 26 Asynchronous Multip...

Page 31: ...T0_i 693 5 80 GPMC_BCH_RESULT1_i 693 5 81 GPMC_BCH_RESULT2_i 693 5 82 GPMC_BCH_RESULT3_i 694 5 83 GPMC_BCH_SWDATA 694 5 84 GPMC_BCH_RESULT4_i 694 5 85 GPMC_BCH_RESULT5_i 695 5 86 GPMC_BCH_RESULT6_i 69...

Page 32: ...Register RI1 745 6 38 HDCP Ri2 Register RI2 746 6 39 HDCP Ri 128 Compare Register RI_128_COMP 746 6 40 HDCP I Counter Register I_CNT 747 6 41 Ri Status Register RI_STAT 747 6 42 Ri Command Register RI...

Page 33: ...ersion B_2_Cb Register B2CB_COEFF_UP 774 6 89 RGB_2_xvYCC Conversion R_2_Cr Register R2CR_COEFF_LOW 775 6 90 RGB_2_xvYCC Conversion R_2_Cr Register R2CR_COEFF_UP 775 6 91 RGB_2_xvYCC Conversion G_2_Cr...

Page 34: ...801 6 133 DDC I2C Target Segment Address Register DDC_SEGM 801 6 134 DDC I2C Target Offset Address Register DDC_OFFSET 801 6 135 DDC I2C Data Count Register DDC_COUNT1 802 6 136 DDC I2C Data Count Re...

Page 35: ...Counter Register I2C_CNT 884 7 32 Data Access Register I2C_DATA 885 7 33 I2C Configuration Register I2C_CON 886 7 34 I2C Own Address Register I2C_OA 888 7 35 I2C Own Address Register I2C_SA 889 7 36 I...

Page 36: ...RC Status Timeout 948 9 16 Read Data Timeout 948 9 17 Boot Acknowledge Timeout When Using CMD0 949 9 18 Boot Acknowledge Timeout When CMD Held Low 949 9 19 Auto CMD12 Timing During Write Transfer 950...

Page 37: ...o Parallel 2 Channel DACs 1015 10 3 McASP to 6 Channel DAC and 2 Channel DAC 1015 10 4 McASP to Digital Amplifier 1016 10 5 McASP as Digital Audio Encoder 1016 10 6 McASP as 16 Channel Digital Process...

Page 38: ...L 1093 10 53 Receive Clock Control Register ACLKRCTL 1094 10 54 Receive High Frequency Clock Control Register AHCLKRCTL 1095 10 55 Receive TDM Time Slot Register RTDM 1096 10 56 Receiver Interrupt Con...

Page 39: ...tion 1140 11 16 Proper Positioning of Receive Frame Sync Pulses 1141 11 17 Unexpected Frame Sync Pulse During a McBSP Transmission 1142 11 18 Proper Positioning of Transmit Frame Sync Pulses 1143 11 1...

Page 40: ...BSP_XCCR_REG 1208 11 73 McBSP_RCCR_REG 1209 11 74 McBSP_XBUFFSTAT_REG 1210 11 75 McBSP_XBUFFSTAT_REG 1210 11 76 McBSP_RBUFFSTAT_REG 1211 11 77 McBSP_RBUFFSTAT_REG 1211 11 78 McBSP_STATUS_REG 1212 12 1...

Page 41: ...STAT 1267 12 33 McSPI Channel i Control Register MCSPI_CH I CTRL 1268 12 34 McSPI Channel i Transmit Register MCSPI_TX i 1269 12 35 McSPI Channel i Receive Register MCSPI_RX i 1269 12 36 McSPI Transf...

Page 42: ...PMRST_ENABLE_SET Register 1328 13 50 PMRST_ENABLE_CLR Register 1328 13 51 OB_OFFSET_INDEXn Register 1329 13 52 OB_OFFSETn_HI Register 1329 13 53 IB_BAR0 Register 1330 13 54 IB_START0_LO Register 1331...

Page 43: ...IMIT Register 1360 13 101 IOSPACE Register 1360 13 102 CAP_PTR Register 1361 13 103 EXPNSN_ROM Register 1361 13 104 BRIDGE_INT Register 1362 13 105 PCIE_CAP Register 1363 13 106 DEVICE_CAP Register 13...

Page 44: ...2 Generic Clock Domain 1400 14 3 Clock Domain State Transitions 1401 14 4 Power Domain Block Diagram 1402 14 5 Device Flying Adder PLLs 1405 14 6 Main FAPLL Interface to PRCM 1411 14 7 DDR FAPLL Inte...

Page 45: ...447 14 50 CM_GEM_CLKSTCTRL Register 1448 14 51 CM_HDDSS_CLKSTCTRL Register 1449 14 52 CM_ACTIVE_GEM_CLKCTRL Register 1451 14 53 CM_ACTIVE_HDDSS_CLKCTRL Register 1452 14 54 CM_DEFAULT_L3_MED_CLKSTCTRL...

Page 46: ...WON_UART_1_CLKCTRL Register 1496 14 100 CM_ALWON_UART_2_CLKCTRL Register 1497 14 101 CM_ALWON_GPIO_0_CLKCTRL Register 1498 14 102 CM_ALWON_GPIO_1_CLKCTRL Register 1499 14 103 CM_ALWON_I2C_0_CLKCTRL Re...

Page 47: ...ARS_REG 1547 15 12 Day of the Week Register WEEKS_REG 1548 15 13 Alarm Second Register ALARM_SECONDS_REG 1548 15 14 Alarm Minute Register ALARM_MINUTES_REG 1549 15 15 Alarm Hour Register ALARM_HOURS_R...

Page 48: ...TA Error Register P SERR 1620 16 31 Port Serial ATA Active Register P SACT 1622 16 32 Port Command Issue Register P CI 1622 16 33 Port Serial ATA Notification Register P SNTF 1623 16 34 Port DMA Contr...

Page 49: ...1 UART to UART Connection With Full Handshaking 1683 19 2 UART Frame Data Format 1683 19 3 UART IrDA to External IR Device 1687 19 4 IrDA SIR Frame Format 1688 19 5 IrDA SIR Encoding Mechanism 1689 19...

Page 50: ...FIFO Line Status Register SFLSR 1732 19 49 RESUME Register 1732 19 50 Status FIFO Register Low SFREGL 1733 19 51 Status FIFO Register High SFREGH 1733 19 52 BOF Control Register BLR 1734 19 53 Auxilia...

Page 51: ...ter EOI 1831 20 25 USBSS IRQ_STATUS_RAW IRQSTATRAW 1832 20 26 USBSS IRQ_STATUS IRQSTAT 1833 20 27 USBSS IRQ_ENABLE_SET Register IRQENABLER 1834 20 28 USBSS IRQ_ENABLE_CLR Register IRQCLEARR 1835 20 29...

Page 52: ...TATUS_RAW_1 Register USB0IRQSTATRAW1 1864 20 72 USB0 IRQ_STATUS_0 Register USB0IRQSTAT0 1865 20 73 USB0 IRQ_STATUS_1 Register USB0IRQSTAT1 1867 20 74 USB0 IRQ_ENABLE_SET_0 Register USB0IRQENABLESET0 1...

Page 53: ...on Count Register 3 FDBSC3 1931 20 124 Queue Manager Free Descriptor Buffer Starvation Count Register 4 FDBSC4 1932 20 125 Queue Manager Free Descriptor Buffer Starvation Count Register 5 FDBSC5 1932...

Page 54: ...1963 20 168 NAKLimit0 Register Host mode only USBn_HOST_NAKLIMIT0 1964 20 169 Transmit Interval Register Host mode only USBn_HOST_TXINTERVAL 1965 20 170 Receive Type Register Host mode only USBn_HOST_...

Page 55: ...e and 8b BCH Encoding 2011 21 16 ECC Data Mapping for 4KB Page and 16b BCH Encoding 2012 21 17 SD Booting 2013 21 18 SD Detection Procedure 2014 21 19 SD Booting Get Booting File 2016 21 20 MBR Detect...

Page 56: ...TUS Field Descriptions 135 1 26 MMU_IRQSTATUS Field Descriptions 136 1 27 MMU_IRQENABLE Field Descriptions 137 1 28 MMU_WALKING_ST Field Descriptions 138 1 29 MMU_CNTL Field Descriptions 138 1 30 MMU_...

Page 57: ...ions 165 1 63 Cortex A8 MPU INTC Interrupt Mapping 171 1 64 Media Controller INTC Interrupt Mapping 174 1 65 DSP INTC Interrupt Mapping 176 1 66 EDMA Regions 179 1 67 EDMA Channel Synchronization Even...

Page 58: ...120 System Status Register SPINLOCK_SYSSTAT Field Descriptions 245 1 121 Lock Register SPINLOCK_LOCK_REG_i Field Descriptions 246 1 122 Integration Attributes 248 1 123 Clocks and Resets 249 1 124 Har...

Page 59: ...escriptions 283 1 171 DDR PLL Frequency 2 Register DDRPLL_FREQ2 Field Descriptions 284 1 172 DDR PLL Divider 2 Register DDRPLL_DIV2 Field Descriptions 284 1 173 DDR PLL Frequency 3 Register DDRPLL_FRE...

Page 60: ...1 217 HD DAC Control Register HD_DAC_CTRL Field Descriptions 317 1 218 HD DAC A Calibration Register HD_DACA_CAL Field Descriptions 318 1 219 HD DAC B Calibration Register HD_DACB_CAL Field Descripti...

Page 61: ...me Treatment Summary 442 3 7 Middle of Frame Overrun Treatment 443 3 8 Emulation Control 454 3 9 EMAC MDIO Registers 455 3 10 EMAC Control Module Registers 455 3 11 EMAC Control Module Identification...

Page 62: ...t Register RXUNICASTSET Field Descriptions 486 3 48 Receive Unicast Clear Register RXUNICASTCLEAR Field Descriptions 487 3 49 Receive Maximum Length Register RXMAXLEN Field Descriptions 488 3 50 Recei...

Page 63: ...26 4 1 GPIO Registers 537 4 2 GPIO_REVISION Register Field Descriptions 538 4 3 GPIO_SYSCONFIG Register Field Descriptions 539 4 4 GPIO_EOI Register Field Descriptions 540 4 5 GPIO_IRQSTATUS_RAW_n Reg...

Page 64: ...elect Configuration 637 5 34 Asynchronous Read and Write Operations 637 5 35 ECC Engine 637 5 36 Prefetch and Write Posting Engine 638 5 37 WAIT Pin Configuration 638 5 38 Enable Chip Select 638 5 39...

Page 65: ...688 5 81 GPMC_ECC_CONTROL Field Descriptions 689 5 82 GPMC_ECC_SIZE_CONFIG Field Descriptions 690 5 83 GPMC_ECCj_RESULT Field Descriptions 692 5 84 GPMC_BCH_RESULT0_i Field Descriptions 693 5 85 GPMC...

Page 66: ...ns 741 6 40 System Control Register 3 SYS_CTRL3 Field Descriptions 741 6 41 Data Control Register DCTL Field Descriptions 742 6 42 HDCP Control Register HDCP_CTRL Field Descriptions 743 6 43 HDCP BKSV...

Page 67: ...on R_2_Cb Register R2CB_COEFF_LOW Field Descriptions 771 6 93 RGB_2_xvYCC Conversion R_2_Cb Register R2CB_COEFF_UP Field Descriptions 772 6 94 RGB_2_xvYCC Conversion G_2_Cb Register G2CB_COEFF_LOW Fie...

Page 68: ...fset2 Register OFFSET2_UP Field Descriptions 799 6 138 xvYCC_2_RGB Conversion DC Level Register DCLEVEL_LOW Field Descriptions 799 6 139 xvYCC_2_RGB Conversion DC Level Register DCLEVEL_UP Field Descr...

Page 69: ...ptions 825 6 189 TEST_TXCTRL Field Descriptions 825 6 190 DPD Field Descriptions 825 6 191 PB_CTRL1 Field Descriptions 826 6 192 PB_CTRL2 Field Descriptions 827 6 193 AVI_TYPE Field Descriptions 828 6...

Page 70: ...241 CEC_RX_COMMAND Field Descriptions 841 6 242 CEC_RX_OPERAND__0 CEC_RX_OPERAND__14 Field Descriptions 842 6 243 HDMI_PHY Registers Summary 843 6 244 TMDS_CNTL2 Field Descriptions 843 6 245 TMDS_CNTL...

Page 71: ...8 1 Interrupt Controller Resets 905 8 2 Interrupt Controller Interrupt Inputs and Outputs 905 8 3 Interrupt Controller INTC Registers 917 8 4 INTCPS_REVISION Register Field Descriptions 918 8 5 INTCP...

Page 72: ...D_HCTL Field Descriptions 985 9 31 SD System Control Register SD_SYSCTL Field Descriptions 988 9 32 Interrupt Status Register SD_STAT Field Descriptions 990 9 33 Interrupt SD Enable Register SD_IE Fie...

Page 73: ...1106 10 37 Transmit Clock Control Register ACLKXCTL Field Descriptions 1107 10 38 Transmit High Frequency Clock Control Register AHCLKXCTL Field Descriptions 1108 10 39 Transmit TDM Time Slot Registe...

Page 74: ...ons 1192 11 37 McBSP_RCERC_REG Field Descriptions 1194 11 38 McBSP_RCERD_REG Field Descriptions 1194 11 39 McBSP_XCERC_REG Field Descriptions 1195 11 40 McBSP_XCERD_REG Field Descriptions 1195 11 41 M...

Page 75: ...ter MCSPI_XFERLEVEL Field Descriptions 1270 13 1 PCIe Transaction Layer Packets Supported 1276 13 2 Example Demonstrating the Mapping of Non contiguous Memories to a Single Region 1281 13 3 Register B...

Page 76: ...US_RAW Register Field Descriptions 1327 13 51 PMRST_IRQ_STATUS Register Field Descriptions 1327 13 52 PMRST_ENABLE_SET Register Field Descriptions 1328 13 53 PMRST_ENABLE_CLR Register Field Descriptio...

Page 77: ...ptions 1356 13 100 BAR1 Register Field Descriptions 1357 13 101 BUSNUM Register Field Descriptions 1357 13 102 SECSTAT Register Field Descriptions 1358 13 103 MEMSPACE Register Field Descriptions 1359...

Page 78: ...Logic Registers 1386 13 148 PL_ACKTIMER Register Field Descriptions 1386 13 149 PL_OMSG Register Field Descriptions 1386 13 150 PL_FORCE_LINK Register Field Descriptions 1387 13 151 ACK_FREQ Register...

Page 79: ...13_CLKSEL Register Field Descriptions 1435 14 42 CM_SYSCLK15_CLKSEL Register Field Descriptions 1436 14 43 CM_VPB3_CLKSEL Register Field Descriptions 1436 14 44 CM_VPC1_CLKSEL Register Field Descripti...

Page 80: ...eld Descriptions 1470 14 88 PM_DEFAULT_PWRSTCTRL Register Field Descriptions 1471 14 89 PM_DEFAULT_PWRSTST Register Field Descriptions 1472 14 90 RM_DEFAULT_RSTCTRL Register Field Descriptions 1473 14...

Page 81: ...CM_ALWON_OCMC_1_CLKCTRL Register Descriptions 1517 14 136 CM_ALWON_CONTRL_CLKCTRL Register Descriptions 1518 14 137 CM_ALWON_GPMC_CLKCTRL Register Descriptions 1519 14 138 CM_ALWON_ETHERNET_0_CLKCTRL...

Page 82: ...rrupt Status Register IS Field Descriptions 1596 16 7 Ports Implemented Register PI Field Descriptions 1597 16 8 AHCI Version Register VS Field Descriptions 1597 16 9 Command Completion Coalescing Con...

Page 83: ...er IRQENABLE Clear Register IRQENABLE_CLR Field Descriptions 1651 17 14 Timer IRQ Wakeup Enable Register IRQWAKEEN Field Descriptions 1652 17 15 Timer Control Register TCLR Field Descriptions 1653 17...

Page 84: ...A Interrupt Identification Register IIR Field Descriptions 1719 19 17 CIR Interrupt Identification Register IIR Field Descriptions 1720 19 18 FIFO Control Register FCR Field Descriptions 1721 19 19 Li...

Page 85: ...it Configuration for Isochronous IN Transactions 1774 20 5 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions 1775 20 6 Isochronous OUT Error Handling Peripheral Mode 1776 20 7 Pac...

Page 86: ...13 Field Descriptions 1844 20 55 USBSS IRQ_DMA_ENABLE_0 Register IRQDMAENABLE0 Field Descriptions 1845 20 56 USBSS IRQ_DMA_ENABLE_1 Register IRQDMAENABLE1 Field Descriptions 1846 20 57 USBSS IRQ_FRAME...

Page 87: ...RQ_EOI Register USB1IRQEOI Field Descriptions 1890 20 104 USB1 IRQ_STATUS_RAW_0 Register USB1IRQSTATRAW1 Field Descriptions 1891 20 105 USB1 IRQ_STATUS_RAW_1 Register USB1IRQSTATRAW1 Field Description...

Page 88: ...Pending Register 4 PEND4 Field Descriptions 1937 20 151 Queue Manager Memory Region R Base Address Register QMEMRBASEr Field Descriptions 1937 20 152 Queue Manager Memory Region R Control Register QM...

Page 89: ...ive Endpoint FIFO Size Register USBn_RXFIFOSZ Field Descriptions 1972 20 195 Transmit Endpoint FIFO Address Register USBn_TXFIFOADDR Field Descriptions 1973 20 196 Receive Endpoint FIFO Address Regist...

Page 90: ...nfiguration 2023 21 24 PCIe 64 BAR Window Size Configuration 2024 21 25 PCIe BAR Window Base Address and Offset Configuration 2024 21 26 Pins Used for UART Boot 2025 21 27 ASIC ID Structure 2025 21 28...

Page 91: ...m to determine the latest version of this TRM Revision History will not be provided for this TRM as long as it is in the Preliminary phase of development Related Documentation From Texas Instruments F...

Page 92: ...92 Read This First SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 93: ...7 1 7 System Memory Map 170 1 8 Device Interrupts 171 1 9 EDMA and EDMA Events 179 1 10 Device Clocking and Flying Adder PLL 182 1 11 Bus Interconnect 199 1 12 Inter Processor Communication 205 1 13 M...

Page 94: ...procedures 1 2 MPU Subsystem 1 2 1 Introduction The Microprocessor Unit MPU subsystem of the device handles transactions between the ARM core ARM Cortex A8 Processor the L3 interconnect and the interr...

Page 95: ...ex A8 1 GHz Preliminary www ti com MPU Subsystem Figure 1 1 Microprocessor Unit MPU Subsystem 1 2 2 Features This section outlines the key features of the MPU subsystem ARM Microprocessor Cortex A8 re...

Page 96: ...D data ram and OCM RAM 1 2 3 MPU Subsystem Integration The MPU subsystem integrates the following group of submodules Cortex A8 Processor Provides a high processing capability including the NEON techn...

Page 97: ...NTC_FIQ MPU subsystem sys_nirq Interrupts INTC PRCM Device CORE_RST MPU_CLK L3_ICLK MPU_RST Non OCP NEON_RST MPU_MSTANDBY Preliminary www ti com MPU Subsystem Figure 1 2 MicroProcessor Unit MPU Subsys...

Page 98: ...ing NEON L2 cache the ETM core emulation and the ARM core AXI2OCP Clock AXI_FCLK This clock is half the frequency of the ARM clock ARM_FCLK The OCP interface thus performs at one half the frequency of...

Page 99: ...ASYNC half bridges are not part of the MPU subsystem Table 1 2 MPU Subsystem Clock Input Signals Clock Signal Maximum Reference source clock Comments Frequency MPU Clock 1 GHz Non Gated SYSCLK2 from P...

Page 100: ...Subsystem www ti com Figure 1 4 Reset Scheme of the MPU Subsystem Table 1 3 Reset Scheme of the MPU Subsystem Signal Name I O Interface MPU_RST I PRCM NEON_RST I PRCM CORE_RST I PRCM MPU_RSTPWRON I PR...

Page 101: ...ARM Cortex A8 Technical Reference Manual Table 1 4 ARM Core supported Features Features Comments ARM version 7 ISA Standard ARM instruction set Thumb2 JazelleX Java accelerator and Media extensions B...

Page 102: ...posite clock domain Bridging to the L3 is accomplished through an asynchronous interface involving the I2Async and T2Async modules The I2Async module inside the MPU subsystem has an OCP port that is a...

Page 103: ...nefill into L1D 4 b1001 Cacheable linefills I D TLB PLE 2 Thread_Mx 5 b01001 1 except linefill into L1D 4 b1010 Cacheable linefills I D TLB PLE 3 Thread_Mx 5 b01010 1 except linefill into L1D 4 b1011...

Page 104: ...o 128 level sensitive interrupts inputs Individual priority for each interrupt input Each interrupt can be steered to nFIQ or nIRQ Independent priority sorting for nFIQ and nIRQ Secure mask flag 1 2 8...

Page 105: ...M NEON accelerator CORE domain MPU interrupt controller EMU domain EMU ETB DAP NOTE L1 and L2 array memories have separate control signals into the in MPU Subsystem thus directly controlled by PRCM Fo...

Page 106: ...etention independently of the other domains Table 1 9 outlines the supported operational power modes All other combinations are illegal The ARM L2 NEON and ETM Debug can be powered up down independent...

Page 107: ...Master Port 1 to L3 Boot Space 1 0x0000_0000 0x00FF_FFFF 1MB L3 0x0000_0000 0x5FFF_FFFF 1 5GB 1MB Tiler 0x6000_0000 0x7FFF_FFFF 256MB 1 2 10 ARM Programming Model For detailed descriptions of registe...

Page 108: ...t through the INTC to wake up the ARM core from STANDBYWFI mode 1 2 10 2 4 MPU Power On From a Powered Off State 1 MPU Power On NEON Power On Core Power On INTC should follow the ordered sequence per...

Page 109: ...and memory controllers for audio processing and general purpose imaging and video processing L1 and L2 shared cache Dedicated enhanced data memory access EDMA engine to download upload data from to m...

Page 110: ...ure based on programmable enhanced version of the C64x DSP core Coprocessor connection through the coprocessor hardware Interface Four instructions per cycle four execution units Optimized instruction...

Page 111: ...for MMU programming and access to DSP internal memories Can be synchronous or asynchronous System interfaces Clocking power management C friendly environment state of the art C compiler for VLIW archi...

Page 112: ...www ti com Figure 1 8 DSP Subsystem Block Diagram 1 3 4 TMS320C674x Megamodule The C674x megamodule Figure 1 7 consists of the following components TMS320C674x CPU Internal memory controllers L1 progr...

Page 113: ...the SRAM Block and global program initiated cache coherence support invalidate Freeze mode 1 3 4 2 L1 Data Memory Controller DMC The DMC reads or writes data from to local memories as requested by th...

Page 114: ...there is a dedicated interface for pipeline write policy management L1 policies are queried at the allocation control of the cache and L2 policies are propagated to the master interface For flexibili...

Page 115: ...signal clear register CHIPSIG_CLR The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG The NMI interrupt is cleared by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR 1 3 4 7 Pow...

Page 116: ...ority driven bandwidth allocation Each requestor EDMA IDMA CPU etc is assigned a priority level on a per transfer basis The programmable priority level has a single meaning throughout the system There...

Page 117: ...s user guide provides a detailed description of System MMU and L2 MMU present in the Media Controller Subsystem For more details on Cortex A8 MMU see the ARM Cortex A8 Core Technical Reference Manual...

Page 118: ...e address translation automatically based on the table entries The table walker automatically retrieves the correct translation table entry for a requested translation If two level translation is used...

Page 119: ...16MB supersection Using bigger page sizes means a smaller translation table Using a smaller page size greatly increases the efficiency of dynamic memory allocation and defragmentation That is why many...

Page 120: ...ies are described in more detail in First Level Translation Table and Two Level Translation 1 4 3 1 2 2 First Level Translation Table The first level translation table describes the translation proper...

Page 121: ...4 23 2 19 18 17 16 15 14 1 11 1 9 2 1 0 0 2 0 X 0 0 Fault Second level Translation Table Base Address X 0 1 Page Section Base Address X 0 M X E X ES X 1 0 Section Super Section base Address X 1 M X E...

Page 122: ...endian Element Size The element size parameter can optionally specify the data access size 8 16 or 32 bits for all data items in the defined section Mixed Region The mixed region parameter specifies w...

Page 123: ...ersection is similar to the translation of a section The difference is that for a supersection only bits 31 to 24 index into the first level translation table The last four bits of the table index are...

Page 124: ...base address of a second level translation table This second level table is indexed by bits 19 to 12 of the virtual address Figure 1 19 Two Level Translation Each second level translation table descr...

Page 125: ...ranslation parameters endianness element size and mixed region have the same meaning as those for sections Table 1 12 Second Level Descriptor Format 31 16 15 12 11 10 9 8 6 5 4 3 2 1 0 X 0 0 Fault Lar...

Page 126: ...Page Translation Summary The translation of a large page is similar to the translation of a small page The difference is that for a large page only bits 19 to 16 index into the second level translati...

Page 127: ...e updated NOTE The last TLB entry Entry N 1 always remains unprotected Figure 1 22 TLB Entry Lock Mechanism The table walking logic automatically writes the TLB entries The entries can also be manuall...

Page 128: ...register This is a system configuration register that controls the various parameters of the L3 interface 1 4 3 3 MMU Software Reset This section describes the software reset feature of the module The...

Page 129: ...TWL disabled 1 4 3 7 MMU Error Handling Table 1 15 Error Handling Item Condition Action 1 Table walk read has an error response Treat generally the same as a translation fault but set the TableWalkFau...

Page 130: ...he following configuration operations are protected against writes during these processes 1 TLB update 2 Global flush 3 Flush entry 4 MMU disable The protection is implemented by stalling the configur...

Page 131: ...interface clock gating MMU_SYSCONFIG 0 AUTOIDLE 0x1 Configure TLB entries Refer to table Configure a TLB Entry Load the physical Address of the page MMU_RAM 31 12 PHYSICALADDRESS 0x Define the endian...

Page 132: ...ogramming Model Value Flush all nonprotected TLB entries MMU_GFLUSH 0 GLOBALFLUSH 0x1 Flush all TLB entries specified by the CAM register MMU_FLUSH_ENTRY 0 FLUSHENTRY 0x1 1 4 4 2 4 Main Sequence Read...

Page 133: ...B RW 32 4Ch MMU_LOCK RW 32 50h MMU_LD_TLB RW 32 54h MMU_CAM RW 32 58h MMU_RAM RW 32 5Ch MMU_GFLUSH RW 32 60h MMU_FLUSH_ENTRY RW 32 64h MMU_READ_CAM R 32 68h MMU_READ_RAM R 32 6Ch MMU_EMU_FAULT_AD R 32...

Page 134: ...y Reads returns 0 4 3 IDLEMODE Idle Mode 0 Force idle An idle request is acknowledged unconditionally 1h No idle An idle request is never acknowledged 2h Smart idle Acknowledgment to an idle request i...

Page 135: ...ESETDONE R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 25 MMU_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reads returns 0 0 RESETDONE Internal rese...

Page 136: ...received during a Table Walk Read 0x0 TableWalkFault false Write 0x0 TableWalkFault status bit unchanged Write 0x1 TableWalkFault status bit is reset Read 0x1 TableWalkFault is true pending 2 EMUMISS...

Page 137: ...asked 1 MultiHitFault event generates an interrupt if occurs 3 TABLEWALKFAULT Error response received during a Table Walk 0 TableWalkFault is masked 1 TableWalkFault event generates an interrupt if oc...

Page 138: ...e 1 29 Figure 1 31 MMU_CNTL 31 4 3 2 1 0 Reserved EMUTLBUPDA TWLENABLE MMUENABLE Reserved TE R 0 R W 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 29 MMU_CNTL Field D...

Page 139: ...0 Write 0 s for future compatibility Reads return 0 1 4 5 2 10 MMU_LOCK The MMU_LOCK register is shown in Figure 1 34 and described in Table 1 32 Figure 1 34 MMU_LOCK 31 15 14 10 9 8 4 3 0 Reserved BA...

Page 140: ...The MMU_CAM register is shown in Figure 1 36 and described in Table 1 34 Figure 1 36 MMU_CAM 31 12 11 4 3 2 1 0 VATAG Reserved P V PAGESIZE R W 0 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read onl...

Page 141: ...6 bits 2h 32 bits 3h No translation 6 MIXED Mixed page attribute use CPU element size 0 Use TLB element size 1 Use CPU element size 5 0 Reserved 0 Write 0 s for future compatibility Reads return 0 1 4...

Page 142: ...he TLB entries specified by the CAM register Read 0x1 never happens 1 4 5 2 16 MMU_READ_CAM The MMU_READ_CAM register is shown in Figure 1 40 and described in Table 1 38 Figure 1 40 MMU_READ_CAM 31 12...

Page 143: ...ld Descriptions Bit Field Value Description 31 12 PHYSICALADDRESS 0 F Physical address of the page FFFFh 11 10 Reserved 0 Reads return 0 9 ENDIANNESS Endianness of the page 0 Little Endian 1 Big endia...

Page 144: ...FFFh 1 4 5 2 19 MMU_FAULT_PC The MMU_FAULT_PC register is shown in Figure 1 43 and described in Table 1 41 Figure 1 43 MMU_FAULT_PC 31 0 PC R 0 LEGEND R W Read Write R Read only n value after reset Ta...

Page 145: ...The 2D 3D graphics accelerator SGX subsystem accelerates 2 dimensional 2D and 3 dimensional 3D graphics applications The SGX subsystem is based on the POWERVR SGX core from Imagination Technologies SG...

Page 146: ...translation from the core virtual address to the external physical address up to 4GB address range Fully virtualized memory addressing for OS operation in a unified memory architecture Advanced and st...

Page 147: ...ces Zero cost swapping in and out of threads Cached program execution model Dedicated pixel processing instructions Dedicated video encode decode instructions SIMD execution unit supporting operations...

Page 148: ...wo clocks an interface clock SGX_ICLK and a functional clock SYSCLK23 The power reset and clock management PRCM module generates and distributes both clocks inside the device Table 1 42 Clock Descript...

Page 149: ...ement The SGX subsystem has its own power domain SGX power domain See the Power Reset and Clock Management chapter for additional information about the SGX power domain As described in the SGX Integra...

Page 150: ...based on the POWERVR SGX530 core from Imagination Technologies The architecture uses programmable and hard coded pipelines to perform various processing tasks required in 2D 3D and video processing T...

Page 151: ...USSE The USSE is a user programmable processing unit Although general in nature its instructions and features are optimized for three types of task processing vertices vertex shading processing pixel...

Page 152: ...ction 1 5 4 1 7 FE34h OCP_IRQSTATUS_1 Interrupt 1 Status Event Register Section 1 5 4 1 8 FE38h OCP_IRQSTATUS_2 Interrupt 2 Status Event Register Section 1 5 4 1 9 FE3Ch OCP_IRQENABLE_SET_0 Enable Int...

Page 153: ...tion Register OCP_HWINFO is shown in Figure 1 48 and described inTable 1 45 Figure 1 48 Hardware Implementation Information Register OCP_HWINFO 31 3 2 1 0 Reserved MEM_BUS_WIDTH SYS_BUS_WIDTH R 0 R 0...

Page 154: ...EGEND R W Read Write R Read only n value after reset Table 1 46 System Configuration Register OCP_SYSCONFIG Field Descriptions Bit Field Value Description 31 6 Reserved 0 Reserved 5 4 STANDBY_MODE Clo...

Page 155: ...Event pending 0 Write No action 1 Write Set event Used for debug 1 5 4 1 5 Raw IRQ 1 Status Register OCP_IRQSTATUS_RAW_1 The Raw IRQ 1 Status Register OCP_IRQSTATUS_RAW_1 is shown in Figure 1 51 and...

Page 156: ...No action 1 Write Set event Used for debug 1 5 4 1 7 Interrupt 0 Status Event Register OCP_IRQSTATUS_0 The Interrupt 0 Status Event Register OCP_IRQSTATUS_0 is shown in Figure 1 53 and described in T...

Page 157: ...pending and interrupt enabled 0 Write No action 1 Write Clear event 1 5 4 1 9 Interrupt 2 Status Event Register OCP_IRQSTATUS_2 The Interrupt 2 Status Event Register OCP_IRQSTATUS_2 is shown in Figure...

Page 158: ...rrupt is disabled 0 Write No action 1 Write Enable interrupt 1 5 4 1 11 Enable Interrupt 1 Register OCP_IRQENABLE_SET_1 The Enable Interrupt 1 Register OCP_IRQENABLE_SET_1 is shown in Figure 1 57 and...

Page 159: ...terrupt is disabled 0 Write No action 1 Write Enable interrupt 1 5 4 1 13 Disable Interrupt 0 Register OCP_IRQENABLE_CLR_0 The Disable Interrupt 0 Register OCP_IRQENABLE_CLR_0 is shown in Figure 1 59...

Page 160: ...Read Interrupt is disabled 0 Write No action 1 Write Disable interrupt 1 5 4 1 15 Disable Interrupt 2 Register OCP_IRQENABLE_CLR_2 The Disable Interrupt 2 Register OCP_IRQENABLE_CLR_2 is shown in Figu...

Page 161: ...Memory Page Register OCP_PAGE_CONFIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 OCP_PAGE_SIZE Defines the page size on OCP memory interface 0 Page size is 4 KB 1h Page...

Page 162: ..._OCP_CMD Invalid command from OCP 0 Read No event pending 1 Read Event pending 0 Write Clear the event 1 Write Set event and interrupt if enabled debug only 9 TARGET_CMD_FIFO_FULL Command FIFO full 0...

Page 163: ...upt if enabled debug only 1 INIT_RESP_UNUSED_TAG Receiving response on an unused tag 0 Read No event pending 1 Read Event pending 0 Write Clear the event 1 Write Set event and interrupt if enabled deb...

Page 164: ...gic 0 Don t Bypass 1 Bypass core interrupt to IO pin ie disregard the interrupt enable setting in IPG register 30 6 Reserved 0 Reserved 5 SELECT_INIT_IDLE To select which idle the disconnect protocol...

Page 165: ...UG_STATUS Field Descriptions Bit Field Value Description 31 CMD_DEBUG_STATE Target command state machine 0 Idle 1 Accept command 30 CMD_RESP_DEBUG_STATE Target response state machine 0 Send accept 1 W...

Page 166: ...rom slave 0 Disconnect request from slave 1 Connect request from slave 9 8 INIT_MCONNECT Initiator MConnect state 0 State is M_OFF 1h State is M_WAIT 2h State is M_DISC 3h State is M_CON 7 6 TARGET_SI...

Page 167: ...ode The pipeline employs an area efficient algorithm that includes a motion adaptive 3D deinterlacer and a non edge adaptive scaler Noise reduction including deringing per pixel motion adaptive tempor...

Page 168: ...riority which determines the display and blending orders Each output supports independent layer visibility control The compositor supports 256 level alpha blending of two overlapping layers The compos...

Page 169: ...or both 59 94 and 60Hz source materials to maintain same output frame rate on both NTSC and HD outputs Video Capture Features The HDVPSS supports two independently configurable external video input ca...

Page 170: ...rts video data write back paths for following Scaled video from aux video channel saved as 422 video Scaled video from main video channel saved as 422 video Independently scaled video from main deinte...

Page 171: ...errupt 14 EDMAERRINT TPCC TPCC error Interrupt 15 Reserved Reserved 16 SATAINT SATA SATA Module interrupt 17 USBSSINT USBSS Queue MGR or CPPI Completion interrupt 18 USBINT0 USBSS RX TX DMA Endpoint r...

Page 172: ...served Reserved 59 Reserved Reserved 60 Reserved Reserved 61 Reserved Reserved 62 Reserved Reserved 63 Reserved Reserved 64 SDINT SD SDIO SDIO interrupt 65 SPIINT McSPI SPI Interrupt 66 Reserved Reser...

Page 173: ...rror interrupt 103 Reserved Reserved 104 Reserved Reserved 105 Reserved Reserved 106 Reserved Reserved 107 Reserved Reserved 108 Reserved Reserved 109 Reserved Reserved 110 Reserved Reserved 111 Reser...

Page 174: ...T Media controller 21 IMPFAULT Media controller 22 CTMINT2 Media controller 23 Reserved Reserved 24 Reserved Reserved 25 TINT1 Timer1 Timer 1 interrupt 26 TINT2 Timer2 Timer 2 interrupt 27 TINT3 Timer...

Page 175: ...SSINT DSS DSS interrupt 62 EDMAINTA TPCC Region 4 DMA completion 63 EDMAINTB TPCC Region 5 DMA completion 64 MACRXTHR0 CPGMAC0 CPGMAC0 Receive threshold interrupt 65 MACRXINT0 CPGMAC0 CPGMAC0 Receive...

Page 176: ...74x 1 event 15 SDINT SD SDIO SD SDIO interrupt 16 SPIINT McSPI SPI Interrupt 17 Reserved Reserved 18 Reserved Reserved 19 Reserved Reserved 20 EDMAINT TPCC Region 1 DMA completion Interrupt 21 EDMAERR...

Page 177: ...IrDA 0 interrupt 61 UARTINT1 UART1 UART IrDA 1 interrupt 62 UARTINT2 UART2 UART IrDA 2 interrupt 63 Reserved Reserved 64 GPIOINT0A GPIO 0 GPIO 0 interrupt 1 65 GPIOINT0B GPIO 0 GPIO 0 interrupt 2 66 G...

Page 178: ...07 Reserved Reserved 108 Reserved Reserved 109 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved 112 Reserved Reserved 113 PMC_ED PMC PMC event 114 Reserved Reserved 115 Reserved Reserved...

Page 179: ...TPCC CFG port 1 9 2 EDMA Regions In order to support multiple processors the TPCC is configured with all eight interrupt regions implemented This allows each processing element Cortex A8 DSP and Medi...

Page 180: ...19 01 0011 SPIREVT1 SPI 20 20 01 0100 SPIXEVT2 SPI 21 21 01 0101 SPIREVT2 SPI 22 22 01 0110 SPIXEVT3 SPI 23 23 01 0111 SPIREVT4 SPI 24 24 01 1000 SDTXEVT SD 25 25 01 1001 SDRXEVT SD 26 26 01 1010 UTXE...

Page 181: ...er 6 51 51 11 0011 TINTEVT7 Timer 7 52 52 11 0100 GPMCEVT GPMC 53 53 11 0101 HDMIEVT HDMI 54 54 11 0110 Unused 55 55 11 0111 Unused 56 56 11 1000 Unused 57 57 11 1001 Unused 58 58 11 1010 I2CTXEVT0 I2...

Page 182: ...igure 1 66 shows a high level overview of the device clocking structure This device requires two primary reference clocks 27 MHz reference clock is required for PLLs These reference clocks sourced fro...

Page 183: ...L3 Interconnect Clock MAINPLL 125 MHz VPDMA Functional SYSCLK4 MAINPLL 500 MHz Clock SYSCLK5 Functional Clock MAINPLL 250 MHz HDVPSS SYSCLK6 Interface Clock MAINPLL 125 MHz HDMI CEC Interface SYSCLK10...

Page 184: ...YSCLK6 MAINPLL 125 MHz Clock HDMI SYSCLK6 Interface Clock MAINPLL 125 MHz Watch Dog Timer SYSCLK6 Interface Clock MAINPLL 125 MHz SYSCLK18 Functional Clock AUDIOPLL 32 768 KHz Interface Functional Mai...

Page 185: ...LL AUDIOPLL SATA McBSP CLKIN1 SERDES_CLKPIN SYSCLK23 SYSCLK6 SYSCLK24 SYSCLK5 SYSCLK1 SYSCLK2 SYSCLK4 SYSCLK6 SYSCLK10 SYSCLK18 SYSCLK18 SYSCLK4 SYSCLK17 SYSCLK11 SYSCLK15 SYSCLK13 SYSCLK18 SYSCLK20 S...

Page 186: ...333 to 533 MHz SYSCLK8 DDR3 333 to 800 MHz SYSCLK8 MTS 27 MHz SYSCLK14 SYSCLK16 MTSI_DLCK EMAC 125 MHz SYSCLK24 EMAC 0 _TXCLK EMAC 0 _RXCLK EMAC 1 _TXCLK EMAC 1 _RXCLK MDIO 25 MHz SYSCLK6 HDVPSS 162 M...

Page 187: ...ives out clock fo The fvco frequency of the PLL is given by fvco N P x fr The fs frequency of the FAPLL is givey by fs fvco x K FREQ The fo frequency of the Post divider is given by fo fs M Where fvco...

Page 188: ...n in Figure 1 69 there are five independently controllable clock outputs asynchronous to each other driven by the main PLL The FREQ and post divider can be tuned independently to control each clock Th...

Page 189: ...SCLK5 Interface Functional MAINPLL 250 MHz Clock OCMCRAM SYSCLK5 Interface Functional MAINPLL 250 MHz Clock UART SYSCLK6 Interface Clock MAINPLL 125 MHz I2C SYSCLK6 Interface Clock MAINPLL 125 MHz SPI...

Page 190: ...0 shows the structure of the DDR PLL An 800 MHz DDR clock is derived directly from the PLL s VCO output divided by 2 Post Divider This clock passes through the RCD Reset Clock Distribution to the IDID...

Page 191: ...enable DDR2 3 controller RCD Preliminary www ti com Device Clocking and Flying Adder PLL Figure 1 70 DDR PLL Structure A good set of frequencies for DDR2 3 can be generated by playing with FREQ and po...

Page 192: ...ier VCO 4 24 FAPLL Post Post PRCM System SYSCLK Reference Divider Output Bits Bits Output Divider Divider Divider Clock Frequency Frequency Frequency Integ Fract Output Domain MHz er ional fr MHz P N...

Page 193: ...z The second one provides SYSCLK13 HD_VENC_D_CLK for the display subsystem HD_VENC_D_CLK needs to support 13 5 MHz 27 MHz 54 MHz 74 25 MHz 148 5 MHz and 161 MHz frequencies The third flying adder synt...

Page 194: ...tion Table 1 79 Example for Video PLL Frequencies Input Pre Multi VCO 4 24 FAPLL Post Post PRCM System Clock SYSCLK Reference Divider plier Output Bits Bits Output Divider Divider Divider Domain Frequ...

Page 195: ...ce and provides a 32 768 KHz clock SYSCLK18 for the SD SDIO peripheral A 32 678 KHz clock for the RTC is sourced from the Control Module This clock has two sources SYSCLK18 and the 32768 Hz clock from...

Page 196: ...16969344 20 45 158484672 1 SYSCLK21 45 158484672 9 3175 1588 1588 1105 92 13 0 5 655 36 20 32 768 1 SYSCLK22 32 768 1105 92 13 0 824 640 4 160 1 SYSCLK19 160 1105 92 11 0 988 738 01801801 5 147 60360...

Page 197: ...hen clear the MAIN_BP bit in MAINPLL_CTRL to 0 to bring MAINPLL out from bypass mode Where x 1 2 3 4 5 Flying Adder Synthesizer 1 10 3 1 7 Changing MAINPLL Multiplier If the MAINPLL is not powered dow...

Page 198: ...xed divided and then passed through a clock gate As shown in Figure 1 73 there are 4 possible sources for clkout one clock from each of the 4 PLLs The selected clock can be further divided by any rati...

Page 199: ...TA used to access the interconnect internal configuration registers Data flow signal Any signal that is part of a clearly identified transfer or data flow typically command address byte enables etc S...

Page 200: ...4 channels 500 MHz R0 W0 R1 W1 R2 W2 R3 W3 BR10 OCPASYNC BR30 OCPASYNC BR31 OCPASYNC BR13 OCPASYNC BR8a OCPASYNC BR14 OCPASYNC BR8 OCP2VBUSM BR27 OCPASYNC BR28 OCPASYNC BR15 I2ASYNC BR21 OCPASYNC BR2...

Page 201: ...SATA 32 bit initiator port Media Controller 64 bit initiator port PCIe 64 bit initiator port Debug Subsystem DAP 32 bit initiator port Graphics accelerator SGX530 128 bit initiator port USB 32 bit CP...

Page 202: ...m MMU 2h Ah SW Media Controller 3h Eh SW TPTC0 Read 6h 18h SW TPTC1 Read 6h 19h SW TPTC2 Read 6h 1Ah SW TPTC3 Read 6h 1Bh SW TPTC0 Write 7h 1Ch SW TPTC1 Write 7h 1Dh SW TPTC2 Write 7h 1Eh SW TPTC3 Wri...

Page 203: ...R R DSS Mstr1 25h R R SGX530 BIF 20h R R R SATA 39h R R R CPGMAC0 Rx Tx 30h R R CPGMAC1 Rx Tx 31h R R USB DMA 34h R R USB Queue Mgr 35h R R R PCIe 3Ah R R R Media Controller Eh R R R EMU DAP 4h R R R...

Page 204: ...Mstr0 24h R DSS Mstr1 25h R SGX530 BIF 20h U SATA 39h R CPGMAC0 Rx Tx 30h R CPGMAC1 Rx Tx 31h R USB DMA 34h USB Queue Mgr 35h R PCIe 3Ah R Media Controller Eh R R R R R R EMU DAP 4h R R R R R R R R R...

Page 205: ...register For implementing efficient Inter Processor Communication between the multiple cores on the device certain hardware features are provided Mailbox interrupts Hardware Spinlocks 1 12 1 Reset Re...

Page 206: ...a mechanism for one processor to write a value to a register and send an interrupt to another processor One system level mailbox is provided for the IPCs between the A8 and the Media M3s The SoC shall...

Page 207: ...www ti com Inter Processor Communication 1 12 3 1 System IPCs Figure 1 76 depicts how Mailbox 1 MBX1 will be used for system IPCs 4 interrupts are generated from the mailbox that allows the A8 C674x...

Page 208: ...sign consideration For example a maximum hold time of less than 200 CPU cycles may be acceptable 2 The locking task cannot be preempted or suspended or interrupted while holding the lock This would ma...

Page 209: ...ilbox module instances in the device System mailbox used for Cortex A8 microprocessor unit Cortex A8 MPU and digital signal processor DSP communications The mailbox module includes the following featu...

Page 210: ..._56 DSP System Mailbox user 1 interrupt 1 13 3 Functional Description This device has the following Mailbox instances System Mailbox Table 1 90 shows Mailbox Implementation in this device where u is t...

Page 211: ...x A8 MPU and DSP through the L3 interconnect iCont1 iCont2 and DSP private access directly through the DSP local interconnect respectively 1 13 3 1 Block Diagram Figure 1 78 shows the mailbox block di...

Page 212: ...k that can cause module interrupts Table 1 92 Interrupt Events Non Maskable Event Maskable Event Flag Event Mask Bit Event Unmask Bit Description Flag 1 MAILBOX_IRQSTATUS MAILBOX_IRQSTATUS MAILBOX_IRQ...

Page 213: ...GSTATUS_m registers Write the message to the corresponding MAILBOX_MESSAGE_m register if space is available The sender might use the queue not full interrupt when the initial mailbox status check indi...

Page 214: ...X_MSGSTATUS_m registers The update of the FIFO queue contents and the associated status registers and possible interrupt generation occurs only when the most significant 16 bits of a MAILBOX_MESSAGE_m...

Page 215: ...ending a Message Polling Method Step Register Bitfield Programming Model Value IF Is FIFO full MAILBOX_FIFOSTATUS_m 0 FIFOFULL 1h MB Wait until at least one message slot is MAILBOX_FIFOSTATUS_m 0 FIFO...

Page 216: ...bes the events servicing in sending mode Table 1 99 Events Servicing in Sending Mode Step Register Bitfield Programming Model Value Read interrupt status bit MAILBOX_IRQSTATUS_CLR_u 1 m 2 1 Write mess...

Page 217: ...ion Register Section 1 13 5 1 0010h MAILBOX_SYSCONFIG Mailbox System Configuration Register Section 1 13 5 2 0040h 4h MAILBOX_MESSAGE_ Mailbox Message Register Section 1 13 5 3 m m 1 0080h 4h MAILBOX_...

Page 218: ...given based on the internal activity of the module based on the internal activity of the module 3 Reserved do not use 1 Reserved 0 Reserved 0 SOFTRESET 0 Soft Hard reset done 1 Reset is ongoing 0 No...

Page 219: ...FIFO queue 1 13 5 4 FIFO Status Register MAILBOX_FIFOSTATUS_m The FIFO status register has the status related to the mailbox internal FIFO The Mailbox FIFO Status Register MAILBOX_FIFOSTATUS_m is sho...

Page 220: ...1 83 Message Status Register MAILBOX_MSGSTATUS_m 31 3 2 0 Reserved NBOFMSGMBM R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 107 Message Status Register MAILBOX_MSGSTATUS_m Fiel...

Page 221: ...STA NOTFULLSTAT NEWMSGSTA NOTFULLSTAT NEWMSGSTA USUUMB3 TUSUUMB3 USUUMB2 TUSUUMB2 USUUMB1 TUSUUMB1 USUUMB0 TUSUUMB0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n...

Page 222: ...event for debug 15 NOTFULLSTATUSUUM Not Full Status bit for User u Mailbox 7 B7 0 Read No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set th...

Page 223: ...Write Set the event for debug 6 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 3 B3 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 224: ...No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set the event for debug 0 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 0 B0 0 Rea...

Page 225: ...LSTAT NEWMSGSTA NOTFULLSTAT NEWMSGSTA USUUMB3 TUSUUMB3 USUUMB2 TUSUUMB2 USUUMB1 TUSUUMB1 USUUMB0 TUSUUMB0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value afte...

Page 226: ...e event for debug 15 NOTFULLSTATUSUUM Not Full Status bit for User u Mailbox 7 B7 0 Read No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set t...

Page 227: ...Write Set the event for debug 6 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 3 B3 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 228: ...No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set the event for debug 0 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 0 B0 0 Re...

Page 229: ...R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 110 IRQ Enable Set Register MAILBOX_IRQENABLE_SET_u Field Descriptions Bit Field Value Description 31 24 Reserved 0 Res...

Page 230: ...rite Set the event for debug 14 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 7 B7 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 231: ...e event for debug 5 NOTFULLSTATUSUUM Not Full Status bit for User u Mailbox 2 B2 0 Read No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set th...

Page 232: ...d Bit Field Value Description 0 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 0 B0 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 233: ...R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 111 IRQ Enable Clear Register MAILBOX_IRQENABLE_CLR_u Field Descriptions Bit Field Value Description 31 24 Reserved 0 Re...

Page 234: ...Write Set the event for debug 14 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 7 B7 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 235: ...he event for debug 5 NOTFULLSTATUSUUM Not Full Status bit for User u Mailbox 2 B2 0 Read No event pending message queue full 1 Read Event pending message queue not full 0 Write No action 1 Write Set t...

Page 236: ...ed Bit Field Value Description 0 NEWMSGSTATUSUUM New Message Status bit for User u Mailbox 0 B0 0 Read No event message pending 1 Read Event message pending 0 Write No action 1 Write Set the event for...

Page 237: ...microprocessor unit MPU subsystem Digital signal processor DSP subsystem Media Controller subsystem The Spinlock module implements 64 spinlocks or hardware semaphores which provide an efficient way to...

Page 238: ...es Attributes Module Instance Power Domain Interconnect SPINLOCK PD_ALWAYS_ON L4_STANDARD Table 1 113 Clocks and Resets Clocks Module Source Signal Destination Signal Name Source Description Instance...

Page 239: ...nt programming between the CLOCKACTIVITY bit and Spinlock clock PRCM control bits The Spinlock module is normally idle except when processing a request from its slave interface port The smart idle mod...

Page 240: ...her process or processor trying to acquire the lock while it is held is small If these conditions are met then the locking code can retry a failed attempt to acquire the lock until success If the cond...

Page 241: ...following table presents the Spinlock initialization after a system bug recovery Software should store 0 into each of the SPINLOCK_LOCK_REG_i registers at system startup to insure that all locks are i...

Page 242: ...pts Critical code section End SPINLOCK_LOCK_REG_i 0 TAKEN 0 Enable all interrupts Take a lock Free a lock Yes No Preliminary Spinlock www ti com Figure 1 91 Take and Release Spinlock 242 Chip Level Re...

Page 243: ...14 5 2 014h SPINLOCK_SYSSTAT System Status Register Section 1 14 5 3 800h 4h i SPINLOCK_LOCK_REG_i Lock Register Section 1 14 5 4 1 14 5 1 Revision Register SPINLOCK_REV The Spin Lock Revision Registe...

Page 244: ...nd may be switched off 1 Interface clock is required by the module even during idle mode 7 5 Reserved 0 Reserved 4 3 SIDLEMODE Slave interface power management IDLE request acknowledgment control 0 Fo...

Page 245: ...s 128 lock registers 8h This instance has 256 lock registers 23 16 Reserved 0 Reserved 15 IU7 0 In Use flag 7 Reads always return 0 14 IU6 0 In Use flag 6 Reads always return 0 13 IU5 0 In Use flag 5...

Page 246: ...ead only n value after reset Table 1 121 Lock Register SPINLOCK_LOCK_REG_i Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 TAKEN Lock State 0 Lock was previously Not Taken fr...

Page 247: ...epends on a programmable configuration parameter 4 8 and 16 bit error correction levels are supported The ELM relies on a static and fixed definition of the generator polynomial for each error correct...

Page 248: ...fly when reading a NAND flash page and stored in GPMC registers are passed to the ELM The microprocessor unit MPU can then correct the data block by flipping the bits to which the ELM error location o...

Page 249: ...LM_SYSSTATUS 0 RESETDONE bit indicates that the software reset is complete when its value is 1 When the software reset completes the ELM_SYSCONFIG 1 SOFTRESET bit is automatically reset 1 15 3 2 ELM P...

Page 250: ...RL i SECTOR_i bits are reset i is the syndrome polynomial number i 0 to 7 continuous mode is used In any other case page mode is implicitly selected Continuous mode Each syndrome polynomial is process...

Page 251: ...olynomial completes its ELM_SYNDROME_FRAGMENT_6_i 16 SYNDROME_VALID bit is reset It must not be set again until the exit status registers ELM_LOCATION_STATUS_i i 0 to 7 for this processing are checked...

Page 252: ...Processing Initialization Step Register Bit Field Programming Model Value Resets the module ELM_SYSCONFIG 1 SOFTRESET 0x1 Wait until reset is done ELM_SYSSTATUS 0 RESETDONE 0x1 Configure the slave in...

Page 253: ...ROME_FRAGMENT_6_i 16 SYNDROME_VALID 0x0 and after the exit status register check ELM_LOCATION_STATUS_i Table 1 130 ELM Processing Completion for Page Mode Step Register Bit Field Programming Model Val...

Page 254: ...00A Initiates the computation process ELM_SYNDROME_FRAGMENT_6_i 16 0x1 SYNDROME_VALID i 0 Wait until process is complete for syndrome polynomial 0 IRQ_ELM is generated or poll the status register Read...

Page 255: ...he 49th byte read from memory It is up to the processor to correctly map this word to the copied buffer and to flip this bit The same process must be repeated for all detected errors 1 15 4 3 Use Case...

Page 256: ...0x0 ELM_SYNDROME_FRAGMENT_2_i i 3 0x0 ELM_SYNDROME_FRAGMENT_3_i i 3 0x0 ELM_SYNDROME_FRAGMENT_4_i i 3 0x0 ELM_SYNDROME_FRAGMENT_5_i i 3 0x0 ELM_SYNDROME_FRAGMENT_6_i i 3 0x0 Initiates the computation...

Page 257: ...2 i 2 1 error detected Read the number of errors for syndrome ELM_LOCATION_STATUS_i 4 0 ECC_NB_ERRORS 0x0 polynomial 3 i 3 0 errors detected Read the error location bit addresses for syndrome ELM_ERR...

Page 258: ...0_i Register Section 1 15 5 8 0_i ELM_SYNDROME_FRAGMENT_ 404h 40h i ELM_SYNDROME_FRAGMENT_1_i Register Section 1 15 5 9 1_i ELM_SYNDROME_FRAGMENT_ 408h 40h i ELM_SYNDROME_FRAGMENT_2_i Register Section...

Page 259: ...ystem Configuration Register ELM_SYSCONFIG Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLOCKACTIVITY OCP Clock activity when module is in IDLE mode during wake up mode pe...

Page 260: ...Read Write R Read only n value after reset Table 1 137 ELM System Status Register ELM_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 Internal reset monitoring OCP...

Page 261: ...d 0 Write No effect 1 Write Clear interrupt 7 LOC_VALID_7 Error location status for syndrome polynomial 7 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0...

Page 262: ...1 Write Clear interrupt 1 LOC_VALID_1 Error location status for syndrome polynomial 1 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0 Write No effect 1 W...

Page 263: ...pt mask bit for syndrome polynomial 7 0 Disable interrupt 1 Enable interrupt 6 LOCATION_MASK_6 Error location interrupt mask bit for syndrome polynomial 6 0 Disable interrupt 1 Enable interrupt 5 LOCA...

Page 264: ...W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 140 ELM Location Configuration Register ELM_LOCATION_CONFIG Field Descriptions Bit Field Value Description 31 27 Reserved 0...

Page 265: ...mode 6 SECTOR_6 0 1 Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode 5 SECTOR_5 0 1 Set to 1 if syndrome polynomial 5 is part of the page in page mode Mu...

Page 266: ...igure 1 105 ELM_SYNDROME_FRAGMENT_1_i Register 31 0 SYNDROME_1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 143 ELM_SYNDROME_FRAGMENT_1_i Register Field Descriptions Bit Field V...

Page 267: ...igure 1 108 ELM_SYNDROME_FRAGMENT_4_i Register 31 0 SYNDROME_4 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 146 ELM_SYNDROME_FRAGMENT_4_i Register Field Descriptions Bit Field V...

Page 268: ...207 1 15 5 15 ELM_LOCATION_STATUS_i Register The ELM_LOCATION_STATUS_i Register is shown in Figure 1 111 and described in Table 1 149 Figure 1 111 ELM_LOCATION_STATUS_i Register 31 9 8 7 5 4 0 Reserve...

Page 269: ...ON_0 15_i Registers 31 13 12 0 Reserved ECC_ERROR_LOCATION R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 150 ELM_ERROR_LOCATION_0 15_i Registers Field Descriptions Bit Field Va...

Page 270: ...e of the functionality of these registers include clock and oscillator control initiator priorities system MMU configuration DDR control register C674x DSP state management USB control and USB PHY con...

Page 271: ...ad only L Latched pin value n value after reset Table 1 152 Control Status Register CONTROL_STATUS Field Descriptions Bit Field Value Description 31 20 Reserved 0 Reserved 19 18 ADMUX GPMC CS0 Default...

Page 272: ...OTSTAT Field Descriptions Bit Field Value Description 31 20 Reserved 0 Reserved 19 16 BOOTERR Boot Error The exact meaning of the various error codes will be determined by the bootloader software 0 No...

Page 273: ...a soft reset The DSP Boot Address Register DSPBOOTADDR is shown in Figure 1 115 and described in Table 1 154 Figure 1 115 5 1 3 DSP Boot Address Register DSPBOOTADDR 31 10 9 1 0 BOOTADDR Reserved RSTD...

Page 274: ...LL Divider 3 Register Section 1 16 1 2 19 460h DDRPLL_FREQ4 DDR PLL Frequency 4 Register Section 1 16 1 2 20 464h DDRPLL_DIV4 DDR PLL Divider 4 Register Section 1 16 1 2 21 468h DDRPLL_FREQ5 DDR PLL F...

Page 275: ...ter reset Table 1 156 Main PLL Control Register MAINPLL_CTRL Field Descriptions Bit Field Value Description 31 16 MAIN_N 0 FFFFh Main PLL N multiplier value 15 8 MAIN_P 0 FFh Main PLL P divider value...

Page 276: ...scriptions Bit Field Value Description 31 8 Reserved 0 Reserved Read returns 0 7 PWD_CLK7 1 0 Main PLL Clock7 Powerdown Setting this bit powers down clock 7 Audio PLL Reference clock 6 PWD_CLK6 1 0 Ma...

Page 277: ...1 1 0 Synth1 Enable Truncate Correction 27 24 MAIN_INTFREQ1 0 Fh Synth1 Frequency integer divider 23 0 MAIN_FRACFREQ1 0 FF FFFFh Synth1 Frequency fractional divider 1 16 1 2 4 Main PLL Divider 1 Regis...

Page 278: ...TRUNC2 1 0 Synth2 Enable Truncate Correction 27 24 MAIN_INTFREQ2 0 Fh Synth2 Frequency integer divider 23 0 MAIN_FRACFREQ2 0 FF FFFFh Synth2 Frequency fractional divider 1 16 1 2 6 Main PLL Divider 2...

Page 279: ...TRUNC4 1 0 Synth4 Enable Truncate Correction 27 24 MAIN_INTFREQ4 0 Fh Synth4 Frequency integer divider 23 0 MAIN_FRACFREQ4 0 FF FFFFh Synth4 Frequency fractional divider 1 16 1 2 8 Main PLL Divider 4...

Page 280: ...eturns 0 28 MAIN_TRUNC5 1 0 Synth5 Enable Truncate Correction 27 24 MAIN_INTFREQ5 0 Fh Synth5 Frequency integer divider 23 0 MAIN_FRACFREQ5 0 FF FFFFh Synth5 Frequency fractional divider 1 16 1 2 10 M...

Page 281: ...to be loaded 7 0 MAIN_MDIV6 0 FFh Frequency M Post Divider6 1 16 1 2 12 Main PLL Divider 7 Register MAINPLL_DIV7 The MAINPLL_DIV7 register is used to control the Main PLL Clock 7 post divider frequenc...

Page 282: ...LEGEND R W Read Write R Read only n value after reset Table 1 168 DDR PLL Control Register DDRPLL_CTRL Field Descriptions Bit Field Value Description 31 16 DDR_N 0 FFFFh DDR PLL N multiplier value 15...

Page 283: ...YSCLK8 2 PWD_CLK2 1 0 DDR PLL Clock2 Powerdown Setting this bit powers down clock 2 SYSCLK9 10 1 PWD_CLK1 1 0 DDR PLL Clock1 Powerdown Setting this bit powers down clock 1 DDR Clock 0 Reserved 0 Reser...

Page 284: ...DR_TRUNC2 1 0 Synth2 Enable Truncate Correction 27 24 DDR_INTFREQ2 0 Fh Synth2 Frequency integer divider 23 0 DDR_FRACFREQ2 0 FF FFFFh Synth2 Frequency fractional divider 1 16 1 2 17 DDR PLL Divider 2...

Page 285: ...DR_TRUNC3 1 0 Synth3 Enable Truncate Correction 27 24 DDR_INTFREQ3 0 Fh Synth3 Frequency integer divider 23 0 DDR_FRACFREQ3 0 FF FFFFh Synth3 Frequency fractional divider 1 16 1 2 19 DDR PLL Divider 3...

Page 286: ...RUNC4 1 0 Synth4 Enable Truncate Correction 27 24 DDR_INTFREQ4 0 Fh Synth4 Frequency integer divider 23 0 DDR_FRACFREQ4 0 FF FFFFh Synth4 Frequency fractional divider 1 16 1 2 21 DDR PLL Divider 4 Reg...

Page 287: ...RUNC5 1 0 Synth5 Enable Truncate Correction 27 24 DDR_INTFREQ5 0 Fh Synth5 Frequency integer divider 23 0 DDR_FRACFREQ5 0 FF FFFFh Synth5 Frequency fractional divider 1 16 1 2 23 DDR PLL Divider 5 Reg...

Page 288: ...R W Read Write R Read only n value after reset Table 1 179 Video PLL Control Register VIDEOPLL_CTRL Field Descriptions Bit Field Value Description 31 16 VIDEO_N 0 FFFFh VIDEO PLL N multiplier value 15...

Page 289: ...nly n value after reset Table 1 180 Video PLL Powerdown Register VIDEOPLL_PWD Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved Read returns 0 3 PWD_CLK3 1 0 Video PLL Clock3 Pow...

Page 290: ...1 0 Synth1 Enable Truncate Correction 27 24 VID_INTFREQ1 0 Fh Synth1 Frequency integer divider 23 0 VID_FRACFREQ1 0 FF FFFFh Synth1 Frequency fractional divider 1 16 1 2 27 Video PLL Divider 1 Regist...

Page 291: ...and FRACFREQ values to be loaded into VIDEO Synthesizer2 30 29 Reserved 0 Reserved Read returns 0 28 VID_TRUNC2 1 0 Synth2 Enable Truncate Correction 27 24 VID_INTFREQ2 0 Fh Synt25 Frequency integer...

Page 292: ...the INTFREQ and FRACFREQ values to be loaded into VIDEO Synthesizer3 30 29 Reserved 0 Reserved Read returns 0 28 VID_TRUNC3 1 0 Synth3 Enable Truncate Correction 27 24 VID_INTFREQ3 0 Fh Synth3 Freque...

Page 293: ...0 R 0 R W 1 R W 1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 187 Audio PLL Control Register AUDIOPLL_CTRL Field Descriptions Bit Field Value Description 31 16 AUDIO_N 0 F...

Page 294: ...t Table 1 188 Audio PLL Powerdown Register AUDIOPLL_PWD Field Descriptions Bit Field Value Description 31 6 Reserved 0 Reserved Read returns 0 5 PWD_CLK4 1 0 AUDIO PLL Clock5 Powerdown Setting this bi...

Page 295: ...C2 1 0 Synth2 Enable Truncate Correction 27 24 AUD_INTFREQ2 0 Fh Synth2 Frequency integer divider 23 0 AUD_FRACFREQ2 0 FF FFFFh Synth2 Frequency fractional divider 1 16 1 2 35 Audio PLL Divider 2 Regi...

Page 296: ...0 Synth3 Enable Truncate Correction 27 24 AUD_INTFREQ3 0 Fh Synth3 Frequency integer divider 23 0 AUD_FRACFREQ3 0 FF FFFFh Synth3 Frequency fractional divider 1 16 1 2 37 Audio PLL Divider 3 Register...

Page 297: ...le Truncate Correction 27 24 AUD_INTFREQ4 0 Fh Synth4 Frequency integer divider 23 0 AUD_FRACFREQ4 0 FF FFFFh Synth4 Frequency fractional divider 1 16 1 2 39 Audio PLL Divider 4 Register AUDIOPLL_DIV4...

Page 298: ...e Truncate Correction 27 24 AUD_INTFREQ5 0 Fh Synth5 Frequency integer divider 23 0 AUD_FRACFREQ5 0 FF FFFFh Synth5 Frequency fractional divider 1 16 1 2 41 Audio PLL Divider 5 Register AUDIOPLL_DIV5...

Page 299: ...l Register Section 1 16 1 3 17 650h DSPMEM_SLEEP DSP L2 Memory Sleep Mode Register Section 1 16 1 3 18 654h OCMEM_SLEEP On Chip Memory Sleep Mode Register Section 1 16 1 3 19 660h HD_DAC_CTRL HD DAC C...

Page 300: ...198 Figure 1 157 Device Identification Register DEVICE_ID 31 28 27 12 11 1 0 DEVREV PARTNUM MFGR Reserved R eFuse R B81Eh R 017h R 1 LEGEND R W Read Write R Read only n value after reset Table 1 198...

Page 301: ...ble 1 199 Initiator Pressure 0 Register INIT_PRESSURE_0 Field Descriptions Bit Field Value Description 31 30 TCWR3 0 3h TPTC 3 Write Port initiator pressure 29 28 TCRD3 0 3h TPTC 3 Read Port initiator...

Page 302: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 200 Initiator Pressure 1 Register INIT_PRESSURE_1 Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 24...

Page 303: ...R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 201 MMU Configuration Register MMU_CFG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved Read retu...

Page 304: ...TC2DBS TC1DBS TC0DBS R W 11 R W 11 R W 11 R W 11 LEGEND R W Read Write R Read only n value after reset Table 1 202 TPTC Configuration Register TPTC_CFG Field Descriptions Bit Field Value Description...

Page 305: ...use the RESETn outputs for the DDR0 and DDR1 interfaces to be held high This allows power down and subsequent power up of EMIFs without resetting DDR devices 27 26 Reserved 0 Reserved Read returns 0 2...

Page 306: ...dby state for debug only 01 No standby mode Initiator is unconditionally removed from standby state for debug only 10 Smart standby mode Initiator standby status depends on local condition module func...

Page 307: ...reset Table 1 205 USB Control Register USB_CTRL Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved Read returns 0 8 PHYCLKSRC USB PHY reference clock source 0 Use PLL reference cl...

Page 308: ...et Table 1 206 USB Phy Control Register 0 USBPHY_CTRL0 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved Read returns 0 30 28 COMPDISTUNE 1 0 Disconnect Threshold Adjust 27 Reserve...

Page 309: ...Control Register 1 USBPHY_CTRL1 Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved Read returns 0 30 28 COMPDISTUNE 1 0 Disconnect Threshold Adjust 27 Reserved 0 Reserved Read retur...

Page 310: ...ddress Byte 1 1 16 1 3 12 Ethernet MAC ID0 High Register MAC_ID0_HI The MAC_ID0_HI register contains the upper 4 bytes of the 48 bit ID for MAC0 The Ethernet MAC ID0 High Register MAC_ID0_HI is shown...

Page 311: ...ddress Byte 1 1 16 1 3 14 Ethernet MAC ID1 High Register MAC_ID1_HI The MAC_ID1_HI register contains the upper 4 bytes of the 48 bit ID for MAC1 The Ethernet MAC ID1 High Register MAC_ID1_HI is shown...

Page 312: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 212 PCIE Configuration Register PCIE_CFG Field Descriptions Bit Field Value Description 31 16 PCIE_CFGPLL 0 FFFFh PCIe PLL Config...

Page 313: ...ol Register CLK_CTL Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved Read returns 0 3 DEVRSELECT Device 27 MHz Oscillator Bias Resistor Controls internal bias resistor connectio...

Page 314: ...X MCB_LBCLKX R 0 R W 0 R W 0 15 3 2 1 0 Reserved ASP2MUTESRC ASP1MUTESRC Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 214 Audio Interface Control Register...

Page 315: ...R 0 15 3 2 1 0 Reserved DSPMEM_SD DSPMEM_DS DSPMEM_LS R 0 R W 1 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 215 DSP L2 Memory Sleep Mode Register DSPMEM_SLEEP Field Descr...

Page 316: ...et Table 1 216 On Chip Memory Sleep Mode Register OCMEM_SLEEP Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved Read returns 0 6 OCM1_SD 1 0 OCM1 Memory in Shutdown Mode Memory c...

Page 317: ...rite R Read only n value after reset Table 1 217 HD DAC Control Register HD_DAC_CTRL Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved Read returns 0 3 HD_CALSEL HD DAC Calibrati...

Page 318: ...e DAC when HD_CALSEL in the HD_DAC_CTRL register is set to 1 1 16 1 3 22 HD DAC B Calibration Register HD_DACB_CAL The HD_DACB_CAL Register is used to calibrate the output level of HD DAC B HD Green P...

Page 319: ...the HD_DAC_CTRL register is set to 1 1 16 1 3 24 SD DAC Control Register SD_DAC_CTRL The SD_DAC_CTRL Register controls operation of the Standard Definition video DACs The SD DAC Control Register SD_D...

Page 320: ...he DAC when SD_CALSEL in the SD_DAC_CTRL register is set to 1 1 16 1 3 26 SD DAC B Calibration Register SD_DACB_CAL The SD_DACB_CAL Register is used to calibrate the output level of SD DAC B SD Green...

Page 321: ...the DAC when SD_CALSEL in the SD_DAC_CTRL register is set to 1 1 16 1 3 28 SD DAC D Calibration Register SD_DACD_CAL The SD_DACD_CAL Register is used to calibrate the output level of SD DAC D SD CVBS...

Page 322: ...ENT1 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 226 HW Event Select Group 1 Register HW_EVT_SEL_GRP1 Field Descriptions Bit Field Value Description 31 30 Reserve...

Page 323: ...ENT1 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 227 HW Event Select Group 2 Register HW_EVT_SEL_GRP2 Field Descriptions Bit Field Value Description 31 30 Reserve...

Page 324: ...ENT1 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 228 HW Event Select Group 3 Register HW_EVT_SEL_GRP3 Field Descriptions Bit Field Value Description 31 30 Reserve...

Page 325: ...ENT1 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 229 HW Event Select Group 4 Register HW_EVT_SEL_GRP4 Field Descriptions Bit Field Value Description 31 30 Reserve...

Page 326: ...de voltage is 1 2 V 1 Common mode voltage is 0 9 V 8 BIAS_TRIM1 1 0 Badgap Reference Trimming bits 7 BIAS_TRIM0 The BIAS_TRIM bits allow the Bandgap voltage to be adjusted when BIAS_TRIMEN is high 00...

Page 327: ...clock input buffer powerdown 0 RCD_PWRDN 1 0 Controls Serdes Reference Clock Distribution powerdown 1 16 1 3 35 USB Clock Control Register USB_CLK_CTL The USB oscillator is controlled by the USB_CLK_...

Page 328: ...n 31 2 Reserved 0 Reserved Read returns 0 1 CML_PWRDN 1 0 PLL Observe clock CML driver powerdown 0 RCD_PWRDN 1 0 PLL Observe clock Reference Clock Distribution powerdown 1 16 1 3 37 DDR RCD Register D...

Page 329: ...ated in the Cortex A8 multiprocessor core alongside Cortex A8 processors It provides 128 hardware interrupt inputs Generation of interrupts by software Prioritization of interrupts Masking of any inte...

Page 330: ...T pin on the device reflects the device reset status The RSTOUT pin remains asserted until PRCM releases the host ARM Cortex A8 processor for reset This output is always asserted when any of the follo...

Page 331: ...c Memory Manager DMM and its Tiling and Isometric Lightweight Engine for Rotation TILER submodule Topic Page 2 1 Introduction 332 2 2 Architecture 335 2 3 Use Case 370 2 4 Registers 385 331 SPRUGX9 15...

Page 332: ...slation MMU like feature The dynamic qualifier for memory management highlights the software configurability and hence the run time nature of the four aspects of memory management handled by the DMM O...

Page 333: ...e priorities required by the SDRAM controller note that these priorities are not used in the DMM One Extra Low Latency Access ELLA having its own interconnect slave port for providing lower latency ac...

Page 334: ...ension Generator Progressive Qualifier for line by line accesses ROBIN Re Ordering Buffer and Initiator Node Tiled access 1D or 2D Access to the tiled area where the image data is read and written in...

Page 335: ...capable of performing tiling conversions Does not interact with the PAT block The ELLA block main role is to split incoming requests at DMM atomic unit boundaries to ensure that requests sent to the S...

Page 336: ...ews which can be bound to one or more initiator through a view mapping mechanism The usage of the Refill Engines is described in detail in the later section 2 2 1 4 1 PAT Views A PAT view defines the...

Page 337: ...ory can be mapped using one LUT With upto 2G of DDR space supported in the Device each LUT entry is 19 bits wide The PAT uses the LUTs only in case of PAT In Direct Access Translation 2 2 1 4 5 PAT Di...

Page 338: ...ing virtual address is interpreted by the PAT is different for 8 bit 16 bit 32 bit mode accesses as compared to the paged mode access described in the preceding section Please refer the TILER section...

Page 339: ...rleaving will happen at the tile boundary of 1KB over riding the interleaving definition of the section For optimal system performance it is recommended to enable interleaving between the 2 EMIF banks...

Page 340: ...tion definition in DMM Figure 2 6 DMM Section and Memory Mapping In Figure 2 6 a request at the system address Addr will follow the interleaving scheme of section 3 although hitting sections 1 2 and 3...

Page 341: ...EMIF0 EMIF1 EMIF0 0x0 to 0xFF 0x0 to 0xFF 0x100 to 0x1FF 0x0 to 0xFF 0x200 to 0x2FF 0x100 to 0x1FF 0x300 to 0x3FF 0x100 to 0x1FF 0x400 to 0x4FF 0x200 to 0x2FF 0x500 to 0x5FF 0x200 to 0x2FF System Byt...

Page 342: ...rtical reflection with no overhead Written differently the functionality of this TILER module is to map a 2D virtually addressed incoming request into one or more physically addressed SDRAM requests b...

Page 343: ...all initiators except HD_VPSS the tiled space is accessed in the 512 MB address range of 6000 0000h to 7FFF FFFFh These initiators use the access the any of 8 views by using the respective DMM_TILER_O...

Page 344: ...n describes address translations that happen at various interfaces within DMM for tiled accesses From a user perspective the PAT can be seen as an additional step in the process applied to the tiled a...

Page 345: ...AT processsing 27 bits 1D or physical address format PAGE TILE SUBTILE PIXEL structure The PAGE field is 15 bits wide Yp Xp 15 bits Yt Xt 2 bits Ys Xs 6 bits Ypx Xpx 4 bits PAGE field TILE field SUBTI...

Page 346: ...ice each memory access can be up to 128 bytes large However because macroblock is not stored contiguously in the memory only partial pixels is useful in each memory access and the rest is discarded an...

Page 347: ...MA engine of HD_VPSS also known as VPDMA has internal line buffers of its capture and display paths called clients For every tiled access it is ensured that rastering tiled data has zero overhead when...

Page 348: ...w 512MiB 90 degree view with horizontal mirror 512MiB Page 4KiB Page sized container 128MiB 32 bit container 128MiB 16 bit container 128MiB 8 bit container 128MiB Tile 1KiB 0 degree view with horizont...

Page 349: ...an be visualized on a 128MB TILER container 2 2 2 2 2 A View is a 512 MB Virtual Address Space Composed of Four Containers There is one container per element size to allow correct access patterns in a...

Page 350: ...s a Cr and Cb 1KB 2x2 8x8 subtiles 1 subtile 2x2 32 bit elements 2 rows of 2 32 bit elements 1 page 4KB 2x8x2 32 pixels 32 bytes 2x8x2 32 pixels 128 bytes Preliminary Architecture www ti com Figure 2...

Page 351: ...i dimensional data locality in a single SDRAM page In this respect it has been sized to 1 KB i e to the size of the smallest SDRAM page Figure 2 18 shows how 4 tiles are arranged in a page This arrang...

Page 352: ...ti com 2 2 2 2 6 A Sub tile is a 128 bit Address Space A 1KB tile is further decomposed into 64 sub tiles each sized 128 bits The sub tile structure is such that it balances accesses in two dimension...

Page 353: ...er can be mapped to either the same physical 128 MB space or at different locations Refer to the PAT_VIEW_MAP register which defines the base address of this 128 MB space As can be seen this base addr...

Page 354: ...ER perspective Bypass mode is for accesses generated by initiators with System addresses outside the virtual tiled address range since TILER will bypass PAT Still at the DMM perspective 2D block burst...

Page 355: ...ive frame in 90 or 270 0 0 16384 Field access to an 8 bit interlaced frame in 90 or 270 8192 Plain access to a 16 bit progressive frame in 90 or 270 1 x x 0 1 16384 Field access to a 16 bit interlaced...

Page 356: ...ode accesses With this scheme up to 128MB of objects can be available simultaneously in 8 16 and 32 bit modes and another 128MB of objects for paged mode accesses Figure 2 24 Using LUT to Translate Ti...

Page 357: ...y 2 2 2 6 2 Container Geometry and Page Mapping Summary The TILER has a page size of 4096 bytes The page Px y has maxx 256 and maxy 128 is found at an offset of 4096 x maxx y bytes from the base addr...

Page 358: ...MB address range of 6000 0000h to 7FFF FFFFh These initiators use the access the any of the 8 views by using the respective DMM_TILER_OR0 or DMM_TILER_OR1 registers 2 For HD_VPSS the TILER module supp...

Page 359: ...which orientation 8 views is used while accessing read and write the data As long as the data is accessed written and read in the same mode it is guaranteed that the response to the access will be cor...

Page 360: ...y to understand how stride is calculated Stride is calculated as the number bytes between pixel m n and pixel m n 1 where m x co ordinate of the image buffer n y co ordinate of the image buffer For S...

Page 361: ...the related orientation In other words Mode is about element granularity Orientation is about change of orthornormal basis for ordering the elements in the mode specific container A corollary to the p...

Page 362: ...ture www ti com 2 2 2 8 4 1 Natural View or 0 View Orientation 0 This orientation defined by S 0 Y 0 and X 0 and means that the operated change of basis is X0 Xn Y0 Yn In any TILER mode the elements a...

Page 363: ...with Vertical Mirror or 180 View with Horizontal Mirror Orientation 1 This orientation defined by S 0 Y 0 and X 1 and means that the operated change of basis is X0 Xn Y0 Yn In any TILER mode the eleme...

Page 364: ...th Horizontal Mirror or 180 View with Vertical Mirror Orientation 2 This orientation defined by S 0 Y 1 and X 0 and means that the operated change of basis is X0 Xn Y0 Yn In any TILER mode the element...

Page 365: ...ry www ti com Architecture 2 2 2 8 4 4 180 View Orientation 3 This orientation defined by S 0 Y 1 and X 1 and means that the operated change of basis is X0 Xn Y0 Yn In any TILER mode the elements are...

Page 366: ...with Vertical Mirror or 270 View with Horizontal Mirror Orientation 4 This orientation defined by S 1 Y 0 and X 0 and means that the operated change of basis is X0 Yn Y0 Xn In any TILER mode the eleme...

Page 367: ...ry www ti com Architecture 2 2 2 8 4 6 270 View Orientation 5 This orientation defined by S 1 Y 0 and X 1 and means that the operated change of basis is X0 Yn Y0 Xn In any TILER mode the elements are...

Page 368: ...nary Architecture www ti com 2 2 2 8 4 7 90 View Orientation 6 This orientation defined by S 1 Y 1 and X 0 and means that the operated change of basis is X0 Yn Y0 Xn In any TILER mode the elements are...

Page 369: ...th Horizontal Mirror or 270 View with Vertical Mirror Orientation 7 This orientation defined by S 1 Y 1 and X 1 and means that the operated change of basis is X0 Yn Y0 Xn In any TILER mode the element...

Page 370: ...SDRAM on one or both the banks Example 1 Symmetrical DDRs on both EMIF banks Each size 512MB to add up to 1GB of total SDRAM memory In all DMM_LISA_MAP__0 3 registers program value 8064 0300h which i...

Page 371: ...Luma buffer and 16 bytes padding in each side for a chroma buffer 5 All buffers are allocated on a 4K aligned address 2 3 2 1 Luma Buffers In 8 bit tiled mode Figure 2 47 each 4K page is arranged as...

Page 372: ...is 960 bytes wide With a pad of 16 bytes on each side the buffer 960 32 992 bytes wide Rounding it to 992 32 1024 so that buffer is allocated on page boundary So one video buffer needs 1024 64 16 page...

Page 373: ...elow 1 Entry table must be in DDR and cannot be split between 2 EMIF banks when data interleaving enabled 2 The data table should start from address 16 byte aligned 3 With one set of descriptor up to...

Page 374: ...1 3 PAT Memory Dump This section presents how to dump the PAT LUT This has to be done using the direct access mode of PAT following the below steps 1 Set at least one of the refill engine to direct L...

Page 375: ...S to start an access to an on going refill area In this case the direction field is set in accordance with the orientation accesses made by the initiators The DMM_PAT_STATUS__x ERROR is asserted to 1...

Page 376: ...d memory mapped descriptor structure where a the next field is set to NULL b the area field is set with the relevant x0 y0 x1 y1 area definition c the ctrl field is set with the requested direction D...

Page 377: ...emory mapped descriptor structures per area where a the next field is set to the physical address of the next descriptor or NULL for the last one b the area field is set with the relevant x0 y0 x1 y1...

Page 378: ...field is set to the physical address of the next descriptor or NULL for the last one b the area field is set with the relevant x0 y0 x1 y1 area definition c the ctrl field is set with the synchronisi...

Page 379: ...res per area where a the next field is set to the physical address of the next descriptor in the circular list b the area field is set with the relevant x0 y0 x1 y1 area definition c the ctrl field is...

Page 380: ...of this parameter is the number of bits actually used in the upper 8 bits of the incoming system address SDRC_ADDR defines the physical base address of the section in the external memory controller SD...

Page 381: ...g eight upper physical address bits All lower address bits are forwarded unchanged 3 If interleaving enabled the physical address generation is modified In case of a 256 bytes interleaving the first c...

Page 382: ...oth EMIF0 and EMIF1 7 0 SDRC_ADDR 0 SDRC address MSB 20h SDRC address MSB NOTE Section 2 and Section 3 are identical to Section 1 How DMM decodes and translates Identical to Section 2 3 4 1 1 See Figu...

Page 383: ...000 0000 EMIF 0 EMIF 1 0x8000 0000 0xC000 0000 0xC7fff ffff System address map 1GB 128MB Section 0 512MB Section 1 64MB Section 0 512MB Section 1 64MB Preliminary www ti com Use Case Figure 2 56 DMM S...

Page 384: ...1 GB 19 18 SDRC_INTL 0 No interleaving 2h 256 bytes interleaving 17 16 SDRC_ADDRSPC 0 Unused Reserved field 0 Unused Reserved field 8 SDRC_MAP 1 Map to EMIF0 3h Map to both EMIF0 and EMIF1 7 0 SDRC_AD...

Page 385: ...04h 534h DMM_PAT_AREA_0 3 Section 2 4 17 508h 538h DMM_PAT_CTRL_0 3 Section 2 4 18 50Ch 53Ch DMM_PAT_DATA_0 3 Section 2 4 19 620h 624h DMM_PEG_PRIO_0 1 Section 2 4 20 640h DMM_PEG_PRIO_PAT Section 2 4...

Page 386: ...kup mode for debug only 2h Smart idle mode local target s idle state eventually follows systems IDLE request 3h Reserved 1 0 Reserved 0 Reserved R 2 4 3 LISA Configuration Locking Register DMM_LISA_LO...

Page 387: ...Reserved 0 Reserved R 22 20 SYS_SIZE DMM system section size R W 0h 16 MB section 1h 32 MB section 2h 64 MB section 3h 128 MB section 4h 256 MB section 5h 512 MB section 6h 1 GB section 7h 2 GB sectio...

Page 388: ...Write enable for OR3 bit field OR3 field is unchanged R W 14 12 OR3 0 Orientation for initiator 8 n 3 R W 11 W2 0 Write enable for OR2 bit field OR2 field is unchanged R W 10 8 OR2 0 Orientation for...

Page 389: ...for V6 bit field V6 field is unchanged R W 26 Reserved 0 Reserved R 25 24 V6 0 PAT view for initiator 8 n 6 R W 23 W5 0 Write enable for V5 bit field V5 field is unchanged R W 22 Reserved 0 Reserved R...

Page 390: ...27 24 CONT_PAGE 0 Base address of Container for page mode or LUT index R W 23 ACCESS_32 Kind of access for this 32 bit mode container R W 0 Direct access container base address given in CONT_32 1 ind...

Page 391: ...0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 15 14 13 12 11 10 9 8 ERR_LUT_ ERR_UPD_ ERR_UPD_ ERR_UPD_ ERR_INV_ ERR_INV_ FILL_LST1 FILL_DSC1 MISS1 DATA1 CTRL1 AREA1 DATA1 DSC1 R W1S 0 R W...

Page 392: ...in area 1 R W1S 12 ERR_UPD_AREA1 0 Area register update whilst refilling error event in area 1 R W1S 11 ERR_INV_DATA1 0 Invalid entry table pointer error event in area 1 R W1S 10 ERR_INV_DSC1 0 Inval...

Page 393: ...te whilst refilling error event in area 3 R W1S 27 ERR_INV_DATA3 0 Invalid entry table pointer error event in area 3 R W1S 26 ERR_INV_DSC3 0 Invalid descriptor pointer error event in area 3 R W1S 25 F...

Page 394: ...in area 0 R W1S 4 ERR_UPD_AREA0 0 Area register update whilst refilling error event in area 0 R W1S 3 ERR_INV_DATA0 0 Invalid entry table pointer error event in area 0 R W1S 2 ERR_INV_DSC0 0 Invalid...

Page 395: ...try table pointer error event in area 3 R W1C 26 ERR_INV_DSC3 0 Invalid descriptor pointer error event in area 3 R W1C 25 FILL_LST3 0 End of refill event for the last descriptor in area 3 R W1C 24 FIL...

Page 396: ...ster update whilst refilling error event in area 0 R W1C 3 ERR_INV_DATA0 0 Invalid entry table pointer error event in area 0 R W1C 2 ERR_INV_DSC0 0 Invalid descriptor pointer error event in area 0 R W...

Page 397: ...ble pointer error event in area 3 R W1S 26 ERR_INV_DSC3 0 Invalid descriptor pointer error event in area 3 R W1S 25 FILL_LST3 0 End of refill event for the last descriptor in area 3 R W1S 24 FILL_DSC3...

Page 398: ...gister update whilst refilling error event in area 0 R W1S 3 ERR_INV_DATA0 0 Invalid entry table pointer error event in area 0 R W1S 2 ERR_INV_DSC0 0 Invalid descriptor pointer error event in area 0 R...

Page 399: ...table pointer error event in area 3 R W1C 26 ERR_INV_DSC3 0 Invalid descriptor pointer error event in area 3 R W1C 25 FILL_LST3 0 End of refill event for the last descriptor in area 3 R W1C 24 FILL_D...

Page 400: ...gister update whilst refilling error event in area 0 R W1C 3 ERR_INV_DATA0 0 Invalid entry table pointer error event in area 0 R W1C 2 ERR_INV_DSC0 0 Invalid descriptor pointer error event in area 0 R...

Page 401: ...re load for engine n R 15 10 ERROR Error occurred in engine n R 0 No error 1h Invalid descriptor provided 2h Invalid data pointer provided 4h Unexpected area register update whilst refilling 8h Unexp...

Page 402: ...ddress of the next table refill descriptor R W 3 0 Reserved 0 Reserved R 2 4 17 DMM PAT Area Geometry Registers DMM_PAT_AREA_0 DMM_PAT_AREA_3 The DMM PAT Area Geometry register is shown and described...

Page 403: ...Reserved R 9 8 LUT_ID 0 PAT LUT index R W 7 Reserved 0 Reserved R 6 4 DIRECTION 0 Direction of this PAT table refill R W 3 1 Reserved 0 Reserved R 0 START 0 Starting a PAT table refill R W 2 4 19 DMM...

Page 404: ...ble for P4 bit field P4 field is updated R W 18 16 P4 4h Priority for initiator 8 n 4 R W 15 W3 0 Write enable for P3 bit field P3 field is updated R W 14 12 P3 4h Priority for initiator 8 n 3 R W 11...

Page 405: ...O module integrated in the device Included are the features of the EMAC and MDIO modules a discussion of their architecture and operation how these modules connect to the outside world and a descripti...

Page 406: ...or fixed priority for transmit quality of service QOS support Ether Stats and 802 3 Stats RMON statistics gathering Transmit CRC generation selectable on a per channel basis Broadcast frames selection...

Page 407: ...arent operation of the MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the networked community The EMAC on...

Page 408: ...ddress A unique 6 byte address that identifies an Ethernet device on the network In an Ethernet packet a MAC address is used twice first to identify the packet s destination and second to identify the...

Page 409: ...s a packet to potentially more than one recipient A group address is specified by setting the LSB of the first MAC address byte to 1 Thus 01h 02h 03h 04h 05h 06h is a valid multicast address Typically...

Page 410: ...K pin For transmit in 1000 Mbps mode the clock is sourced synchronous with the data and is provided by the EMAC to be output on the GMTCLK pin The EMAC module is internally clocked at 148 5 MHz For ti...

Page 411: ...th integrated EMAC and MDIO interfaced via a GMII connection This interface is available in 10 Mbps 100 Mbps and 1000 Mbps modes The GMII interface supports 10 100 1000 Mbps modes Only full duplex mod...

Page 412: ...en both transmit and receive are idle This signal is not necessarily synchronous to EMAC_TXCLK nor EMAC_RXCLK This pin is used in half duplex operation only EMAC_RXCLK I Receive clock EMAC_RXCLK The r...

Page 413: ...ddress that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address This field contains the MAC addr...

Page 414: ...Ethernet devices the port is done with the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 Af...

Page 415: ...ations or is an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data...

Page 416: ...er to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has...

Page 417: ...control module The system configuration determines whether or not an active interrupt actually interrupts the CPU In general the individual interrupts for different events from the EMAC and MDIO must...

Page 418: ...0 Packet Length Example 3 1 Transmit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EM...

Page 419: ...rts on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only...

Page 420: ...re application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit que...

Page 421: ...set this value prior to adding the descriptor to the active receive list This pointer is not altered by the EMAC The value of pNext should never be altered once the descriptor is in an active receive...

Page 422: ..._ALIGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u 3 2 5 5 3 Buffer Offset This 16 bit field must be initialized to zero by the software applica...

Page 423: ...ive queue This bit is set by the EMAC on EOP descriptors 3 2 5 5 8 Ownership OWNER Flag When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software...

Page 424: ...by the EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE 3 2 5 5 17 Overrun Flag This flag is...

Page 425: ...al for allowing the EMAC to operate more independently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read...

Page 426: ...channel s 3 Write the appropriate CPGMAC transmit channel n completion pointer register s TXnCP with the address of the last buffer descriptor of the last packet processed by the application software...

Page 427: ...tor register MACEOIVECTOR in the EMAC module with a value of 3h to signal the end of the miscellaneous interrupt processing 3 2 6 4 Interrupt Pacing The receive and transmit pulse interrupts can be pa...

Page 428: ...s the processor to poll for completion or interrupt the CPU once the operation has completed 3 2 7 1 MDIO Module Components The MDIO module Figure 3 9 interfaces to the PHY components through two MDIO...

Page 429: ...led by default but can be disabled when the connected PHY does not require it Once the MDIO module is enabled the MDIO interface state machine continuously polls the PHY link status by reading the gen...

Page 430: ...e Completion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 in the MDIO user command c...

Page 431: ...on PHY register reads does not follow the procedure outlined in Section 3 2 7 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknow...

Page 432: ...DMA engine receive FIFO and MAC receiver The transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic C...

Page 433: ...ed control logic This enables a packet of 1518 bytes standard Ethernet packet size to be sent without the possibility of underrun The FIFO buffers data in preparation for transmission 3 2 8 1 7 MAC Tr...

Page 434: ...ribes a packet or packet fragment in the system s internal or external memory For receive operations each 16 byte descriptor represents a free packet buffer or buffer fragment On both transmit and rec...

Page 435: ...flow control prevents further frame reception based on the number of free buffers available Receive buffer flow control issues flow control collisions in half duplex mode and IEEE 802 3X pause frames...

Page 436: ...rrently idle or following the completion of the frame currently being transmitted The pause frame contains the maximum possible value for the pause time FFFFh The EMAC counts the receive pause frame t...

Page 437: ...e TXPACE bit is set Adaptive performance pacing introduces delays into the normal transmission of frames delaying transmission attempts between stations reducing the probability of collisions occurrin...

Page 438: ...er immediately is set to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer imme...

Page 439: ...d set to 1 to receive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if...

Page 440: ...mmediately following the protocol type contain the 16 bit TCI field Bits 15 13 of the TCI field contain the received frames priority 0 to 7 The received frame is a low priority frame if the priority v...

Page 441: ...th register RXMAXLEN bytes in length inclusive and contain no code align or CRC errors Received frames are long frames if their frame count exceeds the value in RXMAXLEN The RXMAXLEN reset default val...

Page 442: ...el 0 1 0 0 1 Proper undersized data frames transferred to promiscuous channel 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel 0 1 0 1 1 Proper undersized data and control f...

Page 443: ...t broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 3 7 shows how the overrun condition is handled for the middle of frame overrun Table 3 7 Middle of Fra...

Page 444: ...l teardown The corresponding transmit channel n completion pointer register TXnCP contains the value FFFF FFFCh The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value Ch...

Page 445: ...ls priorities see the device specific data manual 3 2 14 Reset Considerations 3 2 14 1 Software Reset Considerations Peripheral clock and reset control is done through the PRCM module included with th...

Page 446: ...g an interrupt retrigger count based on the peripheral clock SYSCLK5 There is also an 8K block of RAM local to the EMAC that is used to hold packet buffer descriptors Note that although the EMAC contr...

Page 447: ...cControlRegs INTR_COUNT C_RX_IMAX 0x4 4 RX intt ms EmacControlRegs INTR_COUNT C_TX_IMAX 0x4 4 TX intt ms EmacControlRegs CMINTCTRL 0x30000 bit16 bit17 for enabling TX and Rx intt pacing EmacControlReg...

Page 448: ...s The code for this may appear as in Example 3 5 Example 3 5 MDIO Module Initialization Code define PCLK 99 Enable MDIO and setup divider MDIO_REGS CONTROL CSL_FMKT MDIO_CONTROL_ENABLE YES CSL_FMK MDI...

Page 449: ...EEBUFFER receive channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH if buffer flow control is to be enabled 8 Most devic...

Page 450: ...d interrupts may be individually enabled by setting the corresponding bit in the receive interrupt mask set register RXINTMASKSET to 1 Each of the eight channel interrupts may be individually disabled...

Page 451: ...The receive DMA engine has eight channels which each channel having a corresponding interrupt RXPENDn The receive interrupts are level interrupts that remain asserted until cleared by the CPU Each of...

Page 452: ...uffer descriptors results in this error The error bit can only be cleared by resetting the EMAC module in hardware The host error interrupt is enabled by setting the HOSTMASK bit in the MAC interrupt...

Page 453: ...ASKED bit is also set in the MDIO user command complete interrupt register USERINTMASKED The interrupt is cleared by writing back the same bit to USERINTMASKED write to clear 3 2 16 3 Proper Interrupt...

Page 454: ...nformation on the use of the PRCM see the PRCM Reference Guide 3 2 18 Emulation Considerations NOTE For correct operation the EMAC and EMAC control module must both be suspended Thus the EMCONTROL and...

Page 455: ...CONTROL Emulation Control Register Section 3 3 1 3 Ch CMINTCTRL Interrupt Control Register Section 3 3 1 4 10h CMRXTHRESHINTEN Receive Threshold Interrupt Enable Register Section 3 3 1 5 14h CMRXINTEN...

Page 456: ...SS_S_MAJ_VER 0 7h CPGMACSS_S Major Version Value 7 0 CPGMACSS_S_MINOR_VER 0 FFh CPGMACSS_S Minor Version Value 3 3 1 2 EMAC Control Module Software Reset Register CMSOFTRESET The software reset regist...

Page 457: ...bit This bit is used in conjunction with FREE bit to determine the emulation suspend mode This bit has no effect if FREE 1 0 Soft mode is disabled EMAC control module stops immediately during emulati...

Page 458: ...Control Register CMINTCTRL Field Descriptions Bit Field Value Description 31 INT_TEST 0 Interrupt Test Test bit to the interrupt pacing blocks 30 22 Reserved 0 Reserved 21 16 INT_PACE_EN Interrupt Pac...

Page 459: ...responds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on C0_RX_THRESH_PULSE 3 3 1 6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN The receiv...

Page 460: ...interrupt on C0_TX_PULSE 3 3 1 8 EMAC Control Module Miscellaneous Interrupt Enable Register CMMISCINTEN The miscellaneous interrupt enable register CMMISCINTEN is shown in Figure 3 19 and described i...

Page 461: ...RX_THRESH_STAT R 0 R W 0 LEGEND R Read only n value after reset Table 3 19 EMAC Control Module Receive Threshold Interrupt Status Register CMRXTHRESHINTSTAT Field Descriptions Bit Field Value Descript...

Page 462: ...that is enabled and generating an interrupt on C0_RX_PULSE 3 3 1 11 EMAC Control Module Transmit Interrupt Status Register CMTXINTSTAT The transmit interrupt status register CMTXINTSTAT is shown in Fi...

Page 463: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 3 22 EMAC Control Module Miscellaneous Interrupt Status Register CMMISCINTSTAT Field Descriptions Bit Field Value Description 31 4...

Page 464: ...C0_RX_PULSE if pacing is enabled for this interrupt 3 3 1 14 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX The transmit interrupts per millisecond register CMTXINTMAX is...

Page 465: ...lticast Broadcast Promiscuous Channel Enable Section 3 3 2 21 Register 104h RXUNICASTSET Receive Unicast Enable Set Register Section 3 3 2 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section...

Page 466: ...nter Register Section 3 3 2 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 3 3 2 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 3 3 2 47...

Page 467: ...mes Register Section 3 3 2 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 3 3 2 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 3 3 2 50 19 24Ch TXSINGLECOLL Transmi...

Page 468: ...ision code taking the format TXMAJORVER TXMINORVER Ah Current transmit major version value 7 0 TXMINORVER Transmit minor version value Revisions are indicated by a revision code taking the format TXMA...

Page 469: ...Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be t...

Page 470: ...vision code taking the format RXMAJORVER RXMINORVER Ah Current receive major version value 7 0 RXMINORVER Receive minor version value Revisions are indicated by a revision code taking the format RXMAJ...

Page 471: ...ons Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be t...

Page 472: ...ble 3 32 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND...

Page 473: ...ND R Read only n value after reset Table 3 33 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND ma...

Page 474: ...to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrup...

Page 475: ...to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 inte...

Page 476: ...channel 0 15 8 RXTHRESHPEND 0 FFh Receive threshold channels 0 7 interrupt pending RXTHRESHPENDn status bit Bit 8 is receive channel 0 7 0 RXPEND 0 FFh Receive channels 0 7 interrupt pending RXPENDn...

Page 477: ...le 3 38 Receive Interrupt Status Unmasked Register RXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND raw interrupt read before mask 6 RX6PEND 0...

Page 478: ...D R Read only n value after reset Table 3 39 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND mask...

Page 479: ...e channel 7 mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Receiv...

Page 480: ...hannel 7 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Rec...

Page 481: ...Statistics pending interrupt STATPEND raw interrupt read before mask 3 3 2 18 MAC Interrupt Status Masked Register MACINTSTATMASKED The MAC interrupt status masked register MACINTSTATMASKED is shown i...

Page 482: ...1 to enable interrupt a write of 0 has no effect 3 3 2 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 3 45 and described...

Page 483: ...S is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or b...

Page 484: ...to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7...

Page 485: ...lticast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast...

Page 486: ...effect May be read 6 RXCH6EN 0 1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write...

Page 487: ...the enable a write of 0 has no effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable cl...

Page 488: ...ve buffer offset register RXBUFFEROFFSET is shown in Figure 3 50 and described in Table 3 50 Figure 3 50 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGE...

Page 489: ...ue for filtering low priority incoming frames This field should remain 0 if no filtering is desired 3 3 2 27 Receive Channel 0 7 Flow Control Threshold Register RXnFLOWTHRESH The receive channel 0 7 f...

Page 490: ...ree buffers available The RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if re...

Page 491: ...e the third word to any receive buffer descriptor 13 RXOWNERSHIP Receive ownership write bit value 0 EMAC writes the Receive ownership bit to 0 at the end of packet processing 1 EMAC writes the Receiv...

Page 492: ...FERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled Half duplex mode no flow control generated collisions are sent Full duplex mode no outgoing pause frames are sent 1...

Page 493: ...first buffer in a packet but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer descriptor pointer without EOP 4h Zero buffer pointer 5h Zero buffer length 6...

Page 494: ...ceive Quality of Service QOS active bit When asserted indicates that receive quality of service is enabled and that at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the RXF...

Page 495: ...TXCELLTHRESH R 0 R W 24h LEGEND R W Read Write R Read only n value after reset Table 3 57 FIFO Control Register FIFOCONTROL Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reserved 22...

Page 496: ...ster SOFTRESET The soft reset register SOFTRESET is shown in Figure 3 59 and described in Table 3 59 Figure 3 59 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LE...

Page 497: ...3 2 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source address high bytes register MACSRCADDRHI is shown in Figure 3 61 and described in Table 3 61 Figure 3 61 MAC Source Address Hi...

Page 498: ...egister 1 MACHASH1 is shown in Figure 3 62 and described in Table 3 62 Figure 3 62 MAC Hash Address Register 1 MACHASH1 31 16 MACHASH1 R W 0 15 0 MACHASH1 R W 0 LEGEND R Read only R W Read Write n val...

Page 499: ...ented by one for each slot time after the collision 3 3 2 40 Transmit Pacing Algorithm Test Register TPACETEST The transmit pacing algorithm test register TPACETEST is shown in Figure 3 65 and describ...

Page 500: ...e receive pause timer decrements to 0 then another outgoing pause frame is sent and the load decrement process is repeated 3 3 2 42 Transmit Pause Timer Register TXPAUSE The transmit pause timer regis...

Page 501: ...s 0 Address location is not valid and will not be used in determining whether or not an incoming packet matches or is filtered 1 Address location is valid and will be used in determining whether or no...

Page 502: ...d as 0 Therefore only unicast addresses are represented in the address table 3 3 2 45 MAC Index Register MACINDEX The MAC index register MACINDEX is shown in Figure 3 70 and described in Table 3 70 Fi...

Page 503: ...et Host software must initialize these locations to 0 on reset 3 3 2 47 Receive Channel 0 7 DMA Head Descriptor Pointer Register RXnHDP The receive channel 0 7 DMA head descriptor pointer register RXn...

Page 504: ...value written to determine if the interrupt should be deasserted 3 3 2 49 Receive Channel 0 7 Completion Pointer Register RXnCP The receive channel 0 7 completion pointer register RXnCP is shown in Fi...

Page 505: ...l number of good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due t...

Page 506: ...CRC error is defined as having all of the following A frame containing an even number of nibbles Fails the frame check sequence test See Section 3 2 5 5 for definitions of alignment code and CRC error...

Page 507: ...ent code and CRC errors Overruns have no effect on this statistic 3 3 2 50 9 Receive Undersized Frames Register RXUNDERSIZED The total number of undersized frames received on the EMAC An undersized fr...

Page 508: ...eive QOS Filtered Frames Register RXQOSFILTERED The total number of frames received on the EMAC that were filtered due to receive quality of service QOS filtering Such a frame is defined as having all...

Page 509: ...arrier loss and no underrun 3 3 2 50 17 Pause Transmit Frames Register TXPAUSEFRAMES The total number of IEEE 802 3X pause frames transmitted by the EMAC Pause frames cannot underrun or contain a CRC...

Page 510: ...rrun Experienced one collision before successful transmission The collision was not late CRC errors have no effect on this statistic 3 3 2 50 21 Transmit Multiple Collision Frames Register TXMULTICOLL...

Page 511: ...e following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size The carrier sense condition was lost or never asserted when transmitting the frame th...

Page 512: ...llowing Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 256 b...

Page 513: ...the resources to receive it cell FIFO full or no DMA buffer available at the start of the frame CRC errors alignment errors and code errors have no effect on this statistic 3 3 2 50 35 Receive FIFO o...

Page 514: ...MDIO User Command Complete Interrupt Mask Set Register Section 3 3 3 9 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 3 3 3 10 80h USERACCESS0 MDIO User Access R...

Page 515: ...1Fh Highest user channel that is available in the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE P...

Page 516: ...a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY 3 3 3 4 PHY Link S...

Page 517: ...INKINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 LINKINTRAW 0 3h MDIO Link change event raw value When asserted a bit indicates that there was an MDIO link change...

Page 518: ...tion 31 2 Reserved 0 Reserved 1 0 LINKINTMASKED 0 3h MDIO Link change interrupt masked value When asserted a bit indicates that there was an MDIO link change event that is change in the LINK register...

Page 519: ...pt Unmasked Register USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTRAW 0 3h MDIO User command complete event bits When asserted a bit indicates that the...

Page 520: ...e Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKED 0 3h Masked value of MDIO User command complete interrupt When asserted a bit indicates that the previously scheduled PHY read or write command...

Page 521: ...ld Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKSET 0 3h MDIO user interrupt mask set for USERINTMASKED 1 0 respectively Setting a bit to 1 will enable MDIO user command complete interrup...

Page 522: ...er USERINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKCLEAR 0 3h MDIO user command complete interrupt mask clear for USERINTMASKED 1 0 respectively...

Page 523: ...iteable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE...

Page 524: ...ermination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by...

Page 525: ...eable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE W...

Page 526: ...mination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by th...

Page 527: ...Interface This chapter describes the general purpose I O GPIO interface Topic Page 4 1 Introduction 528 4 2 Architecture 530 4 3 Registers 537 527 SPRUGX9 15 April 2011 General Purpose I O GPIO Interf...

Page 528: ...be read from the peripheral bus In Active mode the input line can be used through level and edge detectors to trigger synchronous interrupts The edge rising falling or both or the level logical 0 log...

Page 529: ...control Level detection control Interrupt status register 2 Interrupt status register 1 Interrupt enable2 Interrupt enable1 OR32 I O pins Preliminary www ti com Introduction 4 1 3 Block Diagram Figure...

Page 530: ...e peripheral bus OCP compatible system interface It is used through the entire GPIO module except within the debouncing sub module logic It clocks the OCP interface and the internal logic Clock gating...

Page 531: ...k can be stopped anytime Upon a Sleep mode request issued by the host processor the GPIO module goes to the Idle mode only if there is no active bit in GPIO_IRQSTATUS_RAW_n registers 4 2 2 4 Reset The...

Page 532: ...SET_n registers Due to the sampling operation the minimum pulse width on the input GPIO to trigger a synchronous interrupt request is two times the internally gated interface clock period the internal...

Page 533: ...to 0000 00FFh then a single clock is active NOTE When the clocks are enabled by writing to the GPIO_LEVELDETECT0 GPIO_LEVELDETECT1 GPIO_RISINGDETECT and GPIO_FALLINGDETECT registers the detection star...

Page 534: ...nstruction feature write 0000 0000 0000 0001h at the address of the clear data output register or at the address of the clear interrupt enable register After this write operation a reading of the data...

Page 535: ...f this register with a single write access to the set data output register GPIO_SETDATAOUT or to the clear data output register GPIO_CLEARDATAOUT address If the application uses a pin as an output and...

Page 536: ...drive a low level When a keyboard matrix key is pressed the corresponding row and column lines are shorted together and a low level is driven on the corresponding row channel This generates an interru...

Page 537: ...PIO_IRQSTATUS_CLR_0 Enable Clear Register for Interrupt 1 Section 4 3 7 40h GPIO_IRQSTATUS_CLR_1 Enable Clear Register for Interrupt 2 Section 4 3 7 114h GPIO_SYSSTATUS System Status Register Section...

Page 538: ...MAJOR CUSTOM MINOR R 1 R 0 R 0 R 1 LEGEND R W Read Write R Read only n value after reset Table 4 2 GPIO_REVISION Register Field Descriptions Bit Field Value Description 31 30 SCHEME 1 Used to disting...

Page 539: ...Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 IDLEMODE Power Management Req Ack control 0 Force idle An idle request is acknowledged unconditionally 1h No idle An idle r...

Page 540: ...LEGEND R W Read Write R Read only n value after reset Table 4 4 GPIO_EOI Register Field Descriptions Bits Field Value Description 31 1 Reserved 0 Reserved 0 LINE_NUMBER Software End Of Interrupt EOI...

Page 541: ...t n status 0 No effect 1 IRQ is triggered 4 3 5 GPIO_IRQSTATUS_n Register The GPIO_IRQSTATUS_n register provides core status information for the interrupt handling showing all active events enabled an...

Page 542: ...1 0 INTLINE n Interrupt n enable 0 No effect 1 Enable IRQ generation 4 3 7 GPIO_IRQSTATUS_CLR_n Register All 1 bit fields in the GPIO_IRQSTATUS_CLR_n register clear a specific interrupt event Writing...

Page 543: ...nd described in Table 4 9 Figure 4 14 GPIO_SYSSTATUS Register 31 16 Reserved R 0 15 1 0 Reserved RESETDONE R 0 R 0 LEGEND R Read only n value after reset Table 4 9 GPIO_SYSSTATUS Register Field Descri...

Page 544: ...ic 0 Functional clock is interface clock 1h Functional clock is interface clock divided by 2 2h Functional clock is interface clock divided by 4 3h Functional clock is interface clock divided by 8 0 D...

Page 545: ...LEGEND R Read only n value after reset Table 4 12 GPIO_DATAIN Register Field Descriptions Bits Field Value Description 31 0 DATAIN 0 FFFF FFFFh Sampled Input Data 4 3 12 GPIO_DATAOUT Register The GPIO...

Page 546: ...ect 1 Enable the IRQ assertion on low level detect 4 3 14 GPIO_LEVELDETECT1 Register The GPIO_LEVELDETECT1 register is used to enable disable for each input lines the high level 1 detection to be used...

Page 547: ...edge detect 1 Enable IRQ on rising edge detect 4 3 16 GPIO_FALLINGDETECT Register The GPIO_FALLINGDETECT register is used to enable disable for each input lines the falling edge transition 1 to 0 det...

Page 548: ...NGTIME Register The GPIO_DEBOUNCINGTIME register controls debouncing time the value is global for all ports The debouncing cell is running with the debouncing clock 32 kHz this register represents the...

Page 549: ...UT register 4 3 20 GPIO_SETDATAOUT Register Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the GPIO_DATAOUT register writing a 0 has no effect A read of the GP...

Page 550: ...550 General Purpose I O GPIO Interface SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 551: ...the general purpose memory controller GPMC Topic Page 5 1 Introduction 552 5 2 Architecture 554 5 3 Basic Programming Model 633 5 4 Use Cases And Tips 651 5 5 Registers 663 551 SPRUGX9 15 April 2011...

Page 552: ...s and access schemes Based on the programmed configuration bit fields stored in the GPMC registers the GPMC is able to generate all control signals timing depending on the attached device and access t...

Page 553: ...Interconnect port interface Address NAND access only Control Data Address Chip select configuration Address CS selection Data Preliminary www ti com Introduction Figure 5 1 GPMC Block Diagram 553 SPRU...

Page 554: ...15 0 signal direction control Low during transmit for write access data OUT from GPMC to memory High during receive for read access data IN from memory to GPMC Table 5 2 shows the use of address and d...

Page 555: ...Used A15 D14 D14 Not Used GPMC_D 13 D13 Not Used A14 D13 D13 Not Used GPMC_D 12 D12 Not Used A13 D12 D12 Not Used GPMC_D 11 D11 Not Used A12 D11 D11 Not Used GPMC_D 10 D10 Not Used A11 D10 D10 Not Use...

Page 556: ...ee GPMC external connections options Figure 5 2 shows a connection between the GPMC and a 16 bit synchronous address data multiplexed or AAD multiplexed but this protocol use less address pins externa...

Page 557: ...evice gpmc_d 7 0 gpmc_ncs 7 0 gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_nbe0_cle gpmc_nbe1 gpmc_nwp gpmc_wait 1 0 External device memory D 7 0 nADV ALE WAIT nWE nOE nRE nWP nCS 8 D 7 0 nCS 7 0 nADV ALE nOE...

Page 558: ...TANDBY hardware handshake No wake up request One system direct memory access eDMA request One interrupt request to the Cortex A8 MPU Interrupt Controller MA_IRQ One clock for functional and interface...

Page 559: ...through single or multiple accesses External access profiles single multiple with optimized burst length native or emulated wrap are based on external device characteristics supported protocol bus wi...

Page 560: ...GPMC registers and the finite state machine FSM immediately and unconditionally The GPMC_SYSSTATUS 0 RESETDONE bit indicates that the software reset is complete when its value is 1 The software must e...

Page 561: ...GPMC_DMA_REQ to the eDMA e_DMA_53 5 2 4 6 L3 Slow Interconnect Interface The GPMC L3 Slow interconnect interface is a pipelined interface including an 16 32 bit word write buffer Any system host can...

Page 562: ...it 10b To select an address address data multiplexed device program the following register fields GPMC_CONFIG1_i 11 10 DEVICETYPE field 00 GPMC_CONFIG1_i 9 8 MUXADDDATA bit 01b To select an address da...

Page 563: ...omparison with the address bit line mapping as described in Figure 5 6 with A0 as the device system byte address line Base address is programmed through the GPMC_CONFIG7_i 5 0 BASEADDRESS bit field Th...

Page 564: ...ide device interfacing for both multiplexed and nonmultiplexed protocol It limits the use of 8 bit wide device interfacing to byte alias accesses This limitation is not applicable to NAND device inter...

Page 565: ...al AND combination of PAGEBURSTACCESSTIME timing completion and the wait deasserted state Wait monitoring pipelining is also applicable to multiple accesses access within a page WAIT monitored as acti...

Page 566: ...STIME field WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before WRACCESSTIME completes The advance pipelining of the two GPMC clock cycles is the result of t...

Page 567: ...s In synchronous mode when wait pin monitoring is enabled GPMC_CONFIG1_i 22 WAITREADMONITORING bit the effective access time is a logical AND combination of the RDACCESSTIME timing completion and the...

Page 568: ...ONITORINGTIME 00b or 01b 5 2 4 8 3 5 Wait Monitoring During a Synchronous Write Access During synchronous accesses with wait pin monitoring enabled the WAITWRITEMONITORING bit the wait pin is captured...

Page 569: ...on to data bus in high impedance delay The bus turnaround is a time out counter starting after CS or OE de assertion time whichever occurs first and delays the next access start cycle time The counter...

Page 570: ...read write access Preliminary Architecture www ti com Figure 5 9 Read to Read for an Address Data Multiplexed Device On Different CS Without Bus Turnaround CS0 Attached to Fast Device Figure 5 10 Read...

Page 571: ...PMC_CONFIG1_i 30 READMULTIPLE 0 or GPMC_CONFIG1_i 28 WRITEMULTIPLE 0 All control signals are kept in their default states during these idle GPMC_FCLK cycles This prevents back to back accesses to the...

Page 572: ...cess Chip Select Between the Two Timing Multiplexed SAMECSEN DIFFCSEN Type Type Accesses Parameter Parameter Parameter No idle cycles are inserted R W 0 R W Any Any 0 x if the two accesses are well pi...

Page 573: ...activated during device warm reset and cold reset The global_rst_n pin initializes the internal state machine and the internal configuration registers 5 2 4 8 3 11 Write Protect Signal WP When connect...

Page 574: ...RDCYCLETIME and WRCYCLETIME bit fields can be set with a granularity of 1 or 2 throught GPMC_CONFIG1_i 4 TIMEPARAGRANULARITY When either RDCYCLETIME or WRCYCLETIME completes if they are not already d...

Page 575: ...and byte enable valid hold time control after ADV_ALE de assertion ADVRDOFFTIME and ADVWROFFTIME are applicable to both synchronous and asynchronous modes ADV_ALE signal transitions as controlled thr...

Page 576: ...time to assure proper setup and hold time relative to GPMC_CLK If enabled OEEXTRADELAY applies to all parameters controlling OE_RE transitions OEEXTRADELAY must be used carefully to avoid control sig...

Page 577: ...eassertion times When GPMC_CLK runs at the GPMC_FCLK frequency so that GPMC_CLK edge and control signal transitions refer to the same GPMC_FCLK edge the control signal transitions can be delayed by ha...

Page 578: ...or 2 throught the GPMC_CONFIG1_i 4 TIMEPARAGRANULARITY 5 2 4 9 9 1 Page Burst Access Time on Read Access In asynchronous page read mode the delay between successive word captures in a page is controll...

Page 579: ...ronous and synchronous access see the descriptions of GPMC_CLK RdAccessTime WrAccessTime and wait pin monitoring For more information about timing parameter settings see the sample timing diagrams in...

Page 580: ...When the GPMC generates a read access to an address data multiplexed device it drives the address bus until OE assertion time For details see Section 5 2 4 8 2 3 Address bits A 16 1 from a GPMC perspe...

Page 581: ...me that OE is asserted The end of the access is defined by the GPMC_CONFIG5_i 4 0 RDCYCLETIME parameter In the GPMC when a 16 bit wide device is attached to the controller a 32 bit word write access i...

Page 582: ...ore information see Section 5 2 4 8 2 3 The CS and ADV signals are controlled in the same way as for asynchronous single read operation on an address data multiplexed device Write enable signal WE WE...

Page 583: ...ce Write multiple page access in asynchronous mode is not supported for address data multiplexed devices If GPMC_CONFIG1_i 28 WRITEMULTIPLE is enabled 1 with GPMC_CONFIG1_i 27 WRITETYPE as asynchronou...

Page 584: ...ltiplexed device Address valid signal ADV ADV is asserted and deasserted twice during a read transaction ADV first assertion time is controlled by the GPMC_CONFIG3_i 6 4 ADVAADMUXONTIME field ADV firs...

Page 585: ...MUXONTIME OEAADMUXOFFTIME OEAADMUXONTIME Preliminary www ti com Architecture 5 2 4 10 1 2 3 Asynchronous Single Write Operation on an AAD Multiplexed Device Figure 5 16 shows an asynchronous single wr...

Page 586: ...ts for the first address phase are driven onto the data bus until OE deassertion Data is driven onto the address data bus at the clock edge defined by the GPMC_CONFIG6_i 19 16 WRDATAONADMUXBUS paramet...

Page 587: ...A 16 1 D 15 0 WRDATAONADMUXBUS Preliminary www ti com Architecture 5 2 4 10 2 1 Synchronous Single Read Figure 5 17 and Figure 5 18 show a synchronous single read operation with GPMCFCLKDIVIDER equal...

Page 588: ...eassertion time is controlled by the GPMC_CONFIG2_i 12 8 CSRDOFFTIME field and ensures address hold time to CS deassertion Address valid signal ADV ADV assertion time is controlled by the GPMC_CONFIG3...

Page 589: ...26 24 ADVAADMUXRDOFFTIME field ADV second assertion time is controlled by the GPMC_CONFIG3_i 3 0 ADVONTIME field ADV second deassertion time is controlled by the GPMC_CONFIG3_i 12 8 ADVRDOFFTIME field...

Page 590: ...GEBURSTACCESSTIME PAGEBURSTACCESSTIME Preliminary Architecture www ti com 5 2 4 10 2 2 Synchronous Multiple Burst Read 4 8 16 Word16 Burst With Wraparound Capability Figure 5 19 and Figure 5 20 show a...

Page 591: ...Successive read data are provided by the memory device each one or two GPMC_CLK cycles The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMC_CONFIG1_i 1 0 GPMCFCLKDIVIDER and the memory...

Page 592: ...r synchronous single or burst accesses see Figure 5 21 Figure 5 21 Synchronous Single Write on an Address Data Multiplexed Device When the GPMC generates a write access to an address data multiplexed...

Page 593: ...ronous Multiple Burst Write Synchronous burst write mode provides synchronous single or consecutive accesses Figure 5 22 shows a synchronous burst write access when the chip select is configured in ad...

Page 594: ...e multiple data transactions corresponding to the GPMC_CONFIG5_i 27 24 PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions When the GPMC generates a read access to an address d...

Page 595: ...ion time is controlled by the GPMC_CONFIG4_i 15 13 OEAADMUXOFFTIME field OE second assertion time is controlled by the GPMC_CONFIG4_i 3 0 OEONTIME field OE second deassertion time is controlled by the...

Page 596: ...synchronous Single Read on an Address Data Nonmultiplexed Device The 27 bit address is driven onto the address bus A 27 1 and the 16 bit data is driven onto the data bus D 15 0 Read data is latched at...

Page 597: ...ronous single write operation on a nonmultiplexed device Figure 5 25 Asynchronous Single Write on an Address Data Nonmultiplexed Device The 27 bit address is driven onto the address bus A 27 1 and the...

Page 598: ...zen during the multiple data transactions corresponding to PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions Read data is latched at GPMC_CONFIG5_i 20 16 RDACCESSTIME complet...

Page 599: ...sues only fixed length burst The maximum length that can be issued is defined per CS by the GPMC_CONFIG1_i 24 23 ATTACHEDDEVICEPAGELENGTH field i 0 to 7 When the ATTACHEDDEVICEPAGELENGTH value is less...

Page 600: ...e Synchronous burst read Synchronous burst write not supported by NOR Flash memory pSRAM devices must be powered up and initialized in a predefined manner according to the specifications of the attach...

Page 601: ...e ALE pin asserted After this address phase all operations are streamed and the system requests address is irrelevant To allow correct command address and data access controls the GPMC_CONFIG1_i regis...

Page 602: ...e defined as nonposted A write buffer is used to store write transaction information before the external device is accessed Up to eight consecutive posted write accesses can be accepted and stored in...

Page 603: ...DVWROFFTIME timing parameters WE is controlled by the WEONTIME and WEOFFTIME timing parameters ALE and RE OE are maintained inactive Figure 5 27 shows the NAND command latch cycle CLE is shared with t...

Page 604: ...IME and CSWROFFTIME timing parameters ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters WE is controlled by the WEONTIME and WEOFFTIME timing parameters CLE and RE OE are maintaine...

Page 605: ...n asynchronous read access CS is controlled by the CSONTIME and CSRDOFFTIME timing parameters RE is controlled by the OEONTIME and OEOFFTIME timing parameters To take advantage of RE high to data inva...

Page 606: ...tus read command programming write access If such write to read transactions are used a minimum CS high pulse width must be set For this CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDELAY must be set according...

Page 607: ...ge opening is so long up to 50 s that accesses occurring when the ready pin is sampled inactive can stall GPMC access and eventually cause a system time out If a read access to a NAND flash is done us...

Page 608: ...umn bit parity accumulation This parity accumulation is either accomplished on the programmed number of bytes or 16 bit words read from the memory device or written to the memory device in stream mode...

Page 609: ...16 bit words used for ECC computing accumulation can be selected from between two programmable values The ECCjRESULTSIZE bits j 1 to 9 in the GPMC_ECC_SIZE_CONFIG register select which programmable s...

Page 610: ...bit1 bit0 bit7 bit5 bit3 bit2 bit1 bit7 bit5 bit3 bit2 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 P1o P2o P2o P1o P1o P1o Preliminary Architecture www ti com...

Page 611: ...bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5...

Page 612: ...ations plus one for the spare area are required Results are stored in the GPMC_ECCj_RESULT registers j 1 to 9 Figure 5 34 ECC Computation for a 512 Byte Data Stream Read or Write 5 2 4 12 3 1 4 ECC Co...

Page 613: ...bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0...

Page 614: ...the data is always written read out in the same order BCH relevant accesses are selected by the GPMCs chip select Each page may hold up to 4 Kbytes of data spare bytes not included This means up to 8...

Page 615: ...data message mapping shall follow the following rules Bit endianness within a byte is little endian that is the bytes LS bit is also the lowest degree polynomial parameter a byte b7 b0 with b0 the LS...

Page 616: ...8 Bit Word Byte Offset 4 Bit Most Significant Nibble 4 Bit Less Significant Nibble 1 MSB Nibble S 1 Nibble S 2 2 Nibble S 3 Nibble S 4 S 2 2 Nibble 3 Nibble 2 S 2 1 Nibble 1 Nibble 0 LSB Table 5 17 Mi...

Page 617: ...S 5 Nibble S 6 S 3 2 4 Nibble 2 Nibble 1 Nibble 4 Nibble 3 S 3 2 2 Nibble 0 LSB Note that many other cases exist than the ones represented above for example where the message does not start on a word...

Page 618: ...Section 5 2 4 12 3 3 For each mode A sequence describes the mode in pseudo language with for each section the size and the buffer used for ECC processing if ON The programmable lengths are size size0...

Page 619: ...ocessing ON Repeat with buffer 0 to S 1 size0 nibbles spare processing ON 1 nibble pad spare processing OFF size1 nibbles spare processing OFF Checksum Spare area size nibbles S size0 1 size1 5 2 4 12...

Page 620: ...ON Checksum Spare area size nibbles size0 S 1 size1 5 2 4 12 3 2 13 Mode 0x4 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON One time no buffer used size0 nibbles spar...

Page 621: ...Repeat with buffer 0 to S 1 size0 nibbles spare processing ON Repeat with buffer 0 to S 1 1 nibble padding spare processing OFF size1 nibbles spare processing ON Checksum Spare area size nibbles S siz...

Page 622: ...spare byte section Unprotected by the ECC in nibbles E is the size of the ECC itself in nibbles S is the number of Sectors per page 2 in the current diagrams Each time the processing of a BCH block is...

Page 623: ...r sector spares Spares not covered by ECC ECC right aligned per sector Sector spares Sector spares Sector spares Sector spares size0 Data0 Data1 Prot0 Ecc0 Prot1 Ecc1 Sector spares Sector spares 0 1 0...

Page 624: ...ll ECC at the end left padded size0 size1 size1 size0 size1 size1 Data0 Data1 Protected pooled Ecc0 Ecc1 Pooled page spares 0 1 0 1 0 1 inactive 0 Write Read 7 8 P 1 E P E Mode Size0 Size1 Pooled spar...

Page 625: ...CC at the end left padded Prot0 Prot1 1 0 1 0 ECC size0 Data0 Data1 Sector data non ECC spares 0 1 Read 9 SU E Mode Size0 Size1 Per sector spares separate ECC Spares not covered by ECC All ECC at the...

Page 626: ...other words the prefetch and write posting engine is a single context engine that can be allocated to only one chip select at a time for a read prefetch or a write posting process The engine does not...

Page 627: ...erconnect port can be accessed with Byte 16 bit word or 32 bit word access size according to little endian format even though the FIFO input is 32 bit wide The FIFO control is made easier through the...

Page 628: ...ss phase completion To prevent GPMC stall during this NAND address phase set the STARTENGINE bit field before NAND address phase completion when in synchronized mode The prefetch engine will start whe...

Page 629: ...the prefetch engine is active started and an interrupt is only triggered when COUNTVALUE reaches 0 that is when the prefetch engine automatically goes from an active to an inactive state The number o...

Page 630: ...request when valid data are available from the FIFO and until the programmed GPMC_PREFETCH_CONFIG2 13 0 TRANSFERCOUNT accesses have been completed The STARTENGINE bit clears automatically when posting...

Page 631: ...LCOUNTSTATUS bit is set To clear the interrupt the MPU must clear the TERMINALCOUNTSTATUS bit The TERMINALCOUNTSTATUS bit must always be cleared prior to asserting the TERMINALCOUNTEVENTENABLE bit to...

Page 632: ...his capability is limited to the prefetch and write posting engine accesses and MPU accesses to a NAND memory device through the defined chip select memory region or through the GPMC_NAND_DATA_i where...

Page 633: ...erconnect request is passed in the mean time The engine keeps control of the bus for an additional number of requests programmed in the GPMC_PREFETCH_CONFIG1 19 16 PFPWWEIGHTEDPRIO bit field Control i...

Page 634: ...tion 12 Wait pin configuration 13 Enable chip select 8 NAND chip select configuration 10 ECC engine 9 Read operations asynchronous 9 Write operations asynchronous 11 Prefetch and write posting engine...

Page 635: ...Table 5 33 Write Operations Asynchronous See Table 5 34 Read Operations Asynchronous See Table 5 34 ECC Engine See Table 5 35 Prefetch and Write Posting Engine See Table 5 36 Wait Pin Configuration S...

Page 636: ...r read GPMC_CONFIG1_i 29 READTYPE x operations Set a single or multiple access for write operations GPMC_CONFIG1_i 28 WRITEMULTIPLE x Set a synchronous or asynchronous mode for write GPMC_CONFIG1_i 27...

Page 637: ...gure adequate timing parameters in asynchronous See Section 5 3 6 modes Table 5 35 ECC Engine Sub process Name Register Bitfield Value Select the ECC result register where the first ECC GPMC_ECC_CONTR...

Page 638: ...EFETCH_CONFIG1 5 4 x in synchronized mode WAITPINSELECTOR Enter a number of clock cycles removed to timing GPMC_PREFETCH_CONFIG1 30 28 parameters For all back to back accesses to the NAND x CYCLEOPTIM...

Page 639: ...rite Read Write Page Page Burst Burst Access Access Access Access Access Access Access Access GPMC_CONFIG1_i 30 READMULTIPLE 0 1 N S 0 1 GPMC_CONFIG1_i 29 READTYPE 0 0 N S 1 1 GPMC_CONFIG1_i 28 WRITEM...

Page 640: ...te Access No read access Preliminary Basic Programming Model www ti com 5 3 6 GPMC Timing Parameters Figure 5 43 shows a programming model diagram for the NOR interfacing timing parameters Table 5 41...

Page 641: ...SONTIME y y y y y y y y y y GPMC_CONFIG3_i 30 28 ADVAADMUXWROFFTIME y y y y GPMC_CONFIG3_i 26 24 ADVAADMUXRDOFFTIME y y y y y GPMC_CONFIG3_i 6 4 ADVAADMUXONTIME y y y y y y y y GPMC_CONFIG3_i 20 16 AD...

Page 642: ...ultiplexed multiplexed Access Access Access Access multiplexed access Access Access GPMC_CONFIG6_i 11 8 CYCLE2CYCLEDELAY y y y y y y y y y y GPMC_CONFIG6_i 7 CYCLE2CYCLESAMECSEN y y y y y y y y y y GP...

Page 643: ...invalid H ns Cycle time Write cycle time I ns Delay time GPMC_CS valid to GPMC_OE valid J ns Setup time GPMC_AD 15 0 valid to GPMC_OE invalid K ns Pulse duration GPMC_OE valid time L ns Cycle time Re...

Page 644: ...ter A ns Pulse duration GPMC_CS low B ns Delay time address bus valid to GPMC_CLK first edge Delay time GPMC_BE0_CLE GPMC_BE1 valid to GPMC_CLK first edge C ns Pulse duration GPMC_BE0_CLE GPMC_BE1 low...

Page 645: ...sses For CS falling edge CS activated Case where GPMC_CONFIG1_i 1 0 GPMCFCLKDIVIDER 0x0 F 0 5 CSEXTRADELAY GPMC_FCLK period Case where GPMCFCLKDIVIDER 0x1 F 0 5 CSEXTRADELAY GPMC_FCLK period when CLKA...

Page 646: ...GPMC_FCLK period otherwise Case where GPMCFCLKDIVIDER 0x2 G 0 5 ADVEXTRADELAY GPMC_FCLK period when ADVONTIME CLKACTIVATIONTIME is a multiple of 3 G 1 0 5 ADVEXTRADELAY GPMC_FCLK period when ADVONTIME...

Page 647: ...ed Case where 1 0 GPMCFCLKDIVIDER 0x0 H 0 5 OEEXTRADELAY GPMC_FCLK period Case where GPMCFCLKDIVIDER 0x1 H 0 5 OEEXTRADELAY GPMC_FCLK period when CLKACTIVATIONTIME and OEOFFTIME are odd or CLKACTIVATI...

Page 648: ...MC_FCLK period when WEOFFTIME CLKACTIVATIONTIME 1 is a multiple of 3 I 2 0 5 WEEXTRADELAY GPMC_FCLK period when WEOFFTIME CLKACTIVATIONTIME 2 is a multiple of 3 For GPMC_ADV low pulse duration Read op...

Page 649: ...tion GPMC_BE0_CLE GPMC_BE1 valid time O ns Delay time GPMC_CS valid to GPMC_ADV_ALE valid The configuration parameters are calculated through the following formulas Note that these formulas are not ex...

Page 650: ...BE1 pulse For single read N RDCYCLETIME TIMEPARAGRANULARITY 1 GPMC_FCLK period For burst read N RDCYCLETIME N 1 PAGEBURSTACCESSTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period where N page burst access num...

Page 651: ...h address data multiplexed mode Size 512M bits Data Bus 16 bits wide Speed 104 MHz clock frequency Read access time 80 ns 5 4 1 2 Typical GPMC Setup Table 5 45 lists some of the I Os of the GPMC modul...

Page 652: ...Cases And Tips www ti com Figure 5 47 shows the typical connection between the GPMC module and an attached NOR Flash memory Figure 5 47 GPMC Connection to an External NOR Flash Memory The following se...

Page 653: ...ontroller and its attached device are used to calculate the timing parameters on the GPMC side Read Access time GPMC side Time required to activate the clock read access time requested on the memory s...

Page 654: ...ATIONTIME 1 10 roundmax ClkActivationTime 94 03 9 615 roundmax RdAccessTime ACCESSTIME Ah tIACC DataSetupTime 80 4 415 94 03 9 615 PageBurstAccessTime roundmax tBACC roundmax 5 2 1 PAGEBURSTACCESSTIME...

Page 655: ...cycle tOEZ First on the memory side the external memory makes the data available to the output bus This is the memory side read access time defined in Table 5 49 the number of clock cycles between th...

Page 656: ...n a asynchronous mode AccessTime round max tCE 80 9 ACCESSTIME 9h PageBurstAccessTime n a single access RdCycleTime AccessTime 1cycle tOEZ 96 615 11 RDCYCLETIME Bh CsOnTime tCAS 0 0 CSONTIME 0 CsReadO...

Page 657: ...teristics for Asynchronous Single Write Memory Side AC Characteristics on the Description Duration ns Memory Side tWC Write cycle time 60 tAVDP ADV low time 6 tWP Write pulse width 25 tWPH Write pulse...

Page 658: ...a asynchronous mode Applicable only to AccessTime WAITMONITORING the value is the same as for read access PageBurstAccessTime n a single access WrCycleTime WeOffTime AccessCompletion 57 615 6 WRCYCLE...

Page 659: ...of the GPMC supported memories see Table 5 52 Table 5 52 Supported Memory Interfaces 16 bit 16 bit Address Data Function Address Data OneNAND 16 bit NAND 8 bit NAND Muxed pSRAM or Non Muxed Flash NOR...

Page 660: ...hip Select CS0 Chip Select CE0 Chip Enable CE0 Chip Enable GPMC_CS 1 CS1 CS1 CS1 CE1 CE1 GPMC_CS 2 CS2 CS2 CS2 CE2 CE2 GPMC_CS 3 CS3 CS3 CS3 CE3 CE3 GPMC_CS 4 CS4 CS4 CS4 CE4 CE4 GPMC_CS 5 CS5 CS5 CS5...

Page 661: ...te add input L H L RE H H Data input L L L RE H H Data output L L L H FE x Busy during read x x H H H x Busy during program x x x x x H Busy during erase x x x x x H Write protect x x x x x L Stand by...

Page 662: ...llowing interface protocols when communicating with external memory or external devices Asynchronous read write access Asynchronous read page access 4 8 16 Word16 Synchronous read write access Synchro...

Page 663: ...ion 5 5 14 70h 30h i GPMC_CONFIG5_i 1 Section 5 5 15 74h 30h i GPMC_CONFIG6_i 1 Section 5 5 16 78h 30h i GPMC_CONFIG7_i 1 Section 5 5 17 7Ch 30h i GPMC_NAND_COMMAND_i 1 Section 5 5 18 80h 30h i GPMC_N...

Page 664: ...ead only n value after reset Table 5 57 GPMC_SYSCONFIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 SIDLEMODE Idle mode 0 Force idle An idle request is acknowledged unco...

Page 665: ...0 Reserved RESETDONE R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 58 GPMC_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESETDONE Intern...

Page 666: ...transition on WAIT0 input pin has not been detected W0 WAIT0EDGEDETECTIONSTATUS bit unchanged R1 A transition on WAIT0 input pin has been detected W1 WAIT0EDGEDETECTIONSTATUS bit is reset 7 2 Reserve...

Page 667: ...Wait1 Edge Detection interrupt 0 Wait1EdgeDetection interrupt is masked 1 Wait1EdgeDetection event generates an interrupt if occurs 8 WAIT0EDGEDETECTIONENABLE Enables the Wait0 Edge Detection interrup...

Page 668: ...FCLK cycle and 1FFh corresponds to 511 GPMC FCLK cycles 3 1 Reserved 0 Reserved 0 TIMEOUTENABLE Enable bit of the TimeOut feature 0 TimeOut feature is disabled 1 TimeOut feature is enabled 5 5 7 GPMC_...

Page 669: ...ystem Command of the transaction that caused the error 7 5 Reserved 0 Reserved 4 ERRORNOTSUPPADD Not supported Address error 0 No error occurs 1 The error is due to a non supported Address 3 ERRORNOTS...

Page 670: ...Reserved 9 WAIT1PINPOLARITY Selects the polarity of input pin WAIT1 0 WAIT1 active low 1 WAIT1 active high 8 WAIT0PINPOLARITY Selects the polarity of input pin WAIT0 0 WAIT0 active low 1 WAIT0 active...

Page 671: ...0 Reserved 0 Reserved 9 WAIT1STATUS Is a copy of input pin WAIT1 Reset value is WAIT1 input pin sampled at IC reset 0 WAIT1 asserted inactive state 1 WAIT1 de asserted 8 WAIT0STATUS Is a copy of input...

Page 672: ...wrapping burst 0 Synchronous wrapping burst not supported 1 Synchronous wrapping burst supported 30 READMULTIPLE Selects the read single or multiple access 0 single access 1 multiple access burst if s...

Page 673: ...T0 1h WAIT input pin is WAIT1 2h Reserved 3h Reserved 15 14 Reserved 0 Reserved 13 12 DEVICESIZE Selects the device size attached Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS 0 a...

Page 674: ...R Divides the GPMC FCLK clock 0 GPMC_CLK frequency GPMC_FCLK frequency 1h GPMC_CLK frequency GPMC_FCLK frequency 2 2h GPMC_CLK frequency GPMC_FCLK frequency 3 3h GPMC_CLK frequency GPMC_FCLK frequency...

Page 675: ...for write accesses 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_FCLK cycles 15 13 Reserved 0 Reserved 12 8 CSRDOFFTIME CS de assertion time from start cycle time for read accesses 0 0 GPMC_FCL...

Page 676: ...GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 27 Reserved 0 Reserved 26 24 ADVAADMUXRDOFFTIME ADV assertion for first address phase when using the AAD Mux protocol 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h...

Page 677: ...ress phase when using the AAD Multiplexed protocol 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 3 0 ADVONTIME ADV assertion time from start cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_F...

Page 678: ...Extra Half GPMC FCLK cycle 0 WE Timing control signal is not delayed 1 WE Timing control signal is delayed of half GPMC_FCLK clock cycle 22 20 Reserved 0 Reserved 19 16 WEONTIME WE assertion time fro...

Page 679: ...first address phase in an AAD Multiplexed access 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 3 0 OEONTIME OE assertion time from start cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK...

Page 680: ...URSTACCESSTIME Delay between successive words in a multiple access 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 23 21 Reserved 0 Reserved 20 16 RDACCESSTIME Delay between start cycl...

Page 681: ...Fh Specifies on which GPMC FCLK rising edge the first data of the synchronous burst write is driven in the add data multiplexed bus 15 12 Reserved 0 Reserved 11 8 CYCLE2CYCLEDELAY Chip select high pul...

Page 682: ...ust be avoided as they create holes in the chip select address space 0 Chip select size of 256 Mbytes 8h Chip select size of 128 Mbytes Ch Chip select size of 64 Mbytes Eh Chip select size of 32 Mbyte...

Page 683: ...et Table 5 74 GPMC_NAND_ADDRESS_i Field Descriptions Bit Field Value Description 31 0 GPMC_NAND_ADDRESS_i 0 FFFF FFFFh Writing data at the GPMC_NAND_ADDRESS_i location places the data as the NAND part...

Page 684: ...LK cycle 7h 7 GPMC_FCLK cycles 27 ENABLEOPTIMIZEDACCESS Enables access cycle optimization 0 Access cycle optimization is disabled 1 Access cycle optimization is enabled 26 24 ENGINECSSELECTOR Selects...

Page 685: ...dgeDetection 2h Reserved 3h Reserved 3 SYNCHROMODE Selects when the engine starts the access to CS 0 Engine starts the access to CS as soon as STARTENGINE is set 1 Engine starts the access to CS as so...

Page 686: ...00h 8 Kbytes 5 5 23 GPMC_PREFETCH_CONTROL Figure 5 73 GPMC_PREFETCH_CONTROL 31 16 Reserved R 0 15 1 0 Reserved STARTENGINE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 78 GP...

Page 687: ...laces to be written 23 17 Reserved 0 Reserved 16 FIFOTHRESHOLDSTATUS Set when FIFOPointer exceeds FIFOThreshold value 0 FIFOPointer smaller or equal to FIFOThreshold Writing to this bit has no effect...

Page 688: ...to 16 bits error correction t 16 3h Reserved 11 8 ECCWRAPMODE 0 Fh Spare area organization definition for the BCH algorithm See the BCH syndrome parity calculator module functional specification for...

Page 689: ...amic position of the ECC pointer Writes to this field select the ECC result register where the first ECC computation will be stored Writing values not listed disables the ECC engine ECCEnable bit of G...

Page 690: ...Bytes 1h 4 Bytes 2h 6 Bytes 3h 8 Bytes FFh 512 Bytes 21 20 Reserved 0 Reserved 19 12 ECCSIZE0 Defines ECC size 0 0 2 Bytes 1h 4 Bytes 2h 6 Bytes 3h 8 Bytes FFh 512 Bytes 11 9 Reserved 0 Reserved 8 ECC...

Page 691: ...C3RESULTSIZE Selects ECC size for ECC 3 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 1 ECC2RESULTSIZE Selects ECC size for ECC 2 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 0 EC...

Page 692: ...0 1 Odd Row Parity bit 256 23 P128O 0 1 Odd Row Parity bit 128 22 P64O 0 1 Odd Row Parity bit 64 21 P32O 0 1 Odd Row Parity bit 32 20 P16O 0 1 Odd Row Parity bit 16 19 P8O 0 1 Odd Row Parity bit 8 18...

Page 693: ...ND R W Read Write R Read only n value after reset Table 5 85 GPMC_BCH_RESULT1_i Field Descriptions Bit Field Value Description 31 0 BCH_RESULT1_i 0 FFFF FFFFh BCH ECC result bits 32 to 63 5 5 31 GPMC_...

Page 694: ...ad Write R Read only n value after reset Table 5 88 GPMC_BCH_SWDATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BCH_DATA 0 FFFFh Data to be included in the BCH calcul...

Page 695: ...ULT5_i 0 FFFF FFFFh BCH ECC result bits 160 to 191 5 5 36 GPMC_BCH_RESULT6_i Figure 5 86 GPMC_BCH_RESULT6_i 31 0 BCH_RESULT6_i R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 91 GP...

Page 696: ...696 General Purpose Memory Controller GPMC SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 697: ...MI This chapter describes the high definition multimedia interface HDMI module Topic Page 6 1 Introduction 698 6 2 Architecture 702 6 3 Registers 718 697 SPRUGX9 15 April 2011 High Definition Multimed...

Page 698: ...P module contains the support logic for the HDMI IP including the HDMI core HDMI_CORE and CEC core The major additional parts comprise a slave interface port for configuration and buffering for the au...

Page 699: ...or data island support Integrated TMDS physical layer PHY three TMDS differential data lanes TMDS differential clock lane Up to 1 85625 Gbps per lane at 1080p at 60 Hz at 10 bits component lower resol...

Page 700: ...880 x 480p 1280 x 720p 60 Hz 1440 x 480p 1440 x 480i 720 x 480p 640 x 480p Table 6 2 HDMI Video Timings VESA DMT Refresh Rate Resolution 640 x 480p 800 x 600p 848 x 480p 1024 x 768p 1280 x 768p 1280 x...

Page 701: ...odule HDMI complex input output I O HDMI_TXPHY The VPSS module provides synchronization signals to the HDMI and synchronously sends 30 bits of pixel data to the HDMI with these signals The digital out...

Page 702: ...he frequency of the DSS_L3_ICLK clock generated by the device PRCM module and is asynchronous with the other clocks TCLK clock domain Runs at the frequency of the TMDS clock TMDS_CLK generated by the...

Page 703: ..._ddc_scl I O DDC I2C clock line DDC clock input output hdmi_ddc_sda I O DDC I2C clock line DDC clock input output 1 I Input O Output 6 2 3 Integration This section describes the module integration in...

Page 704: ...re www ti com Figure 6 4 HDMI Integration NOTE For more information about the IDLE hardware handshake and the wake up request see Sleep Idle and Wake Up Management in Power Reset and Clock Management...

Page 705: ...Interrupt Request HDMI DSS_HDMI_DMA EDMA_53 EDMA HDMI audio DMA request 6 2 5 Power Management Table 6 8 describes the power management features available to the HDMI module NOTE For information abou...

Page 706: ...e to identify the interrupt event s NOTE The HDMI_WP_IRQENABLE_SET register is used to enable the interrupt event s by writing 1 in the desired bit field s To disable the interrupt event s the HDMI_WP...

Page 707: ...VPSS_DATA 29 HDMI_VIDEO_DATA 35 R11 R8 VPSS_DATA 28 HDMI_VIDEO_DATA 34 R10 R7 VPSS_DATA 27 HDMI_VIDEO_DATA 33 R9 R6 VPSS_DATA 26 HDMI_VIDEO_DATA 32 R8 R5 VPSS_DATA 25 HDMI_VIDEO_DATA 31 R7 R4 VPSS_DA...

Page 708: ...rt data bus HDMI_WP_VIDEO_CFG 10 8 PACKING_MODE 1 If 8 bit deep color mode is not selected and RGB format is used on the video port data bus HDMI_WP_VIDEO_CFG 10 8 PACKING_MODE 7h If 12 bit deep color...

Page 709: ...e thresholds The DMA IRQ is generated when the number of samples 24 or 16 bit in the FIFO is less than or equal to the threshold value The size of samples is selected through the HDMI_WP_AUDIO_CFG 0 S...

Page 710: ...DMA transfer length The threshold is not set to the correct value in the HDMI_WP_AUDIO_CTRL 8 0 TRESHOLD_VALUE bit field The device MPU module does not check the filling of the FIFO when the audio da...

Page 711: ...l 3 4 Unused Left Channel 1 5 Unused Right Channel 2 6 Unused Center Channel 3 24 bits 8 channels right justified 1 Unused Left Channel 1 2 Unused Right Channel 2 3 Unused Left Channel 3 4 Unused Righ...

Page 712: ...Ah FRC FLC RC FC FR FL 1Bh FRC FLC RC FC LFE FR FL 1Ch FRC FLC RR RL FR FL 1Dh FRC FLC RR RL LFE FR FL 1Eh FRC FLC RR RL FC FR FL 1Fh FRC FLC RR RL FC LFE FR FL 20h FCH RR RL FC FR FL 21h FCH RR RL FC...

Page 713: ...le must be filled with 0 depending on the audio format The HDMI_WP_AUDIO_CFG 23 16 AUDIO_CHANNEL_LOCATION bit field indicates the location and the active channels The AUDIO_CHANNEL_LOCATION field cont...

Page 714: ...ut may be overridden based on the audio FIFO operation forced to invalid if FIFO data is invalid They may also be forced to valid or invalid This format supports only two channels stereo or two monoph...

Page 715: ...daptation is done to optimize the audio data transfer There are three different formats in the audio FIFO Two L PCM samples on 16 bits in a 32 bit container One L PCM sample on 24 bits in a 32 bit con...

Page 716: ...connect The maximum data rate supported is 1 85625 Gbps per data lane The lane module function and position are configurable That is any lane module can be chosen as a clock or a data lane module and...

Page 717: ...ting YCbCr data and outputting full range 0 255 RGB PC mode data across HDMI When outputting limited range 16 235 RGB CE mode data across the link clear RANGE to 0 Set WIDE_BUS to the number of bits p...

Page 718: ...per video 70h HDMI_WP_CLK Configuration of clocks 80h HDMI_WP_AUDIO_CFG Audio Configuration in FIFO 84h HDMI_WP_AUDIO_CFG2 Audio configuration of DMA 88h HDMI_WP_AUDIO_CTRL Audio FIFO control 8Ch HDMI...

Page 719: ...of the IP module s internal requirements Backup mode for debug only 1h No idle mode local target never enters idle state Used in case Audio is transferred to avoid DSS_L3_ICLK clock to be shut down 2h...

Page 720: ...TUS_RAW Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 AUDIO_FIFO_SAMPLE_REQ_INTR Settable raw status for audio events R0 No event pending W0 No action R1 IRQ event pendin...

Page 721: ...tinued Bit Field Value Description 0 CORE_INTR Settable raw status for HDMI Core interrupt R0 Software reset done no pending action W0 No action R1 Software reset ongoing W1 Set event 721 SPRUGX9 15 A...

Page 722: ...ATUS Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 AUDIO_FIFO_SAMPLE_REQ_INTR R0 No event pending W0 No action R1 IRQ event pending W1 Set event 9 AUDIO_FIFO_OVERFLOW_INT...

Page 723: ...ved 10 ENABLE_SET_AUDIO_FIFO_ Enable for audio interrupt events for sample request Generated only SAMPLE_REQ_INTR in IRQ mode instead of DMA mode default value R0 Interrupt disabled W0 No action R1 In...

Page 724: ...ued Bit Field Value Description 0 ENABLE_SET_CORE_INTR Enable for audio interrupt events for core interrupt R0 Interrupt disabled W0 No action R1 Interrupt enabled W1 Enable interrupt 724 High Definit...

Page 725: ...e after reset Table 6 23 Interrupt Disable Register HDMI_WP_IRQENABLE_CLEAR Field Descriptions Bit Field Value Description 31 11 Reserved 0 Reserved 10 ENABLE_CLEAR_AUDIO_FIFO_ R0 Interrupt disabled S...

Page 726: ...R Field Descriptions continued Bit Field Value Description 0 ENABLE_CLEAR_CORE_INTR R0 Interrupt disabled W0 No action R1 Interrupt enabled W1 Enable interrupt 726 High Definition Multimedia Interface...

Page 727: ...r for line 5v short input Default value is 20 in decimal 0 Disabled 1 3Fh From 1 63 size of the glitch filtered based on OCP clock frequency 6 3 1 8 Configuration of HDMI Wrapper Video Register HDMI_W...

Page 728: ...ed to pack 20 bits YUV422 input data in case the video input is not already packed Will pack video_data 35 28 video_data 23 16 video_data 11 10 video_data 7 6 7h No change on input video_data lines Th...

Page 729: ...ME_OUT_DIS Timeout in case CEC_DDC_CLK not provided 0 Timeout after 4095 OCP clock cycles after inactivity HDMI Core register interface due to CEC_DDC_CLK not provided to HDMI An interrupt is generate...

Page 730: ...nabled in the HDMI_core module 4h 4 stereo channels enabled in the HDMI_core module 23 16 AUDIO_CHANNEL_LOCATION 3h This field contains which channels are active It is used also to define which regist...

Page 731: ...criptions continued Bit Field Value Description 0 SAMPLE_SIZE Audio sample size 16 bits or 24 bits not applicable if IEC format 0 Sample is on 16 bits 1 Sample is on 24 bits 731 SPRUGX9 15 April 2011...

Page 732: ...1 and described in Table 6 29 Figure 6 21 Audio FIFO Control Register HDMI_WP_AUDIO_CTRL 31 30 29 26 25 24 WRAPPER_ CORE_REQ_ Reserved NUMBER_OF_SAMPLE ENABLE ENABLE R W R W R 0h R 0h 23 16 NUMBER_OF_...

Page 733: ...equal to the threshold value The max threshold is 511 and min 0 6 3 1 13 TX Data of FIFO Register HDMI_WP_AUDIO_DATA The TX data of FIFO register is shown in Figure 6 22 and described in Table 6 30 F...

Page 734: ...s A8h RI_RX_H Ri From RX Registers ACh RI_DEBUG Ri Debug Registers C8h DE_DLY VIDEO DE Delay Register C8h DE_DLY VIDEO DE Delay Register CCh DE_CTRL VIDEO DE Control Register D0h DE_TOP VIDEO DE Top R...

Page 735: ...er 178h R2CR_COEFF_UP RGB_2_xvYCC Conversion R_2_Cr Register 17Ch G2CR_COEFF_LOW RGB_2_xvYCC Conversion G_2_Cr Register 180h G2CR_COEFF_UP RGB_2_xvYCC Conversion G_2_Cr Register 184h B2CR_COEFF_LOW RG...

Page 736: ...CC_2_RGB Conversion DC Level Register 28Ch DCLEVEL_UP xvYCC_2_RGB Conversion DC Level Register 3B0h DDC_MAN DDC I2C Manual Register 3B4h DDC_ADDR DDC I2C Target Slave Address Register 3B8h DDC_SEGM DD...

Page 737: ...value after reset Table 6 34 Device IDL Register DEV_IDL Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 DEV_ID Device ID low byte Provides unique vendor identification through I2C...

Page 738: ...Read only n value after reset Table 6 36 Device Revision Register DEV_REV Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 DEV_REV Allows distinction between revisions of same devi...

Page 739: ...em Control Register 1 SYS_CTRL1 The system control register 1 is shown in Figure 6 29 and described in Table 6 38 Figure 6 29 System Control Register 1 SYS_CTRL1 31 16 Reserved R 0h 15 8 Reserved R 0h...

Page 740: ...a Bus 1 24 bit Data Bus 1 EDGE Edge select 0 Latch Input on Falling Edge 1 Latch Input on Rising Edge 0 PD Power down mode HIGH is normal operation When LOW interrupts are in power down mode Most othe...

Page 741: ...ed on 1 HPD X Hot plug detect The state of the hot plug detect pin can be read here 0 P_STABLE X IDCK io_pclkpin to TMDS clock v_ck2x is stable and the Transmitter can send reliable data on the TMDS l...

Page 742: ...erved 2 VID_BLANK 0 Normal operation video output is not blanked 1 Video output is blanked and the colors sent are those specified in registers VID_BLANK1 VID_BLANK2 and VID_BLANK3 1 AUD_MUTE 0 Do not...

Page 743: ...e This is a necessary step in the computation of shared values in the HDCP protocol For more information sefer section 2 2 in the HDCP 1 0 Specification 0 Single HDMI Receiver 1 HDMI Receiver is a Rep...

Page 744: ...BKSV__0 BKSV__4 Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 BKSV Write Written with the HDCP receiver key selection vector register value Writing 5th BKSV byte triggers the au...

Page 745: ...SV Register AKSV__0 AKSV__4 Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 AKSV HDCP capable transmitter s key selection vector 5th AKSV byte triggers the authentication logic in...

Page 746: ...i 128 compare register is shown in Figure 6 39 and described in Table 6 48 Figure 6 39 HDCP Ri 128 Compare Register RI_128_COMP 31 7 6 0 Reserved RI_128_COMP R 0h R 0h LEGEND R W Read Write R Read onl...

Page 747: ...ite R Read only n value after reset Table 6 50 Ri Status Register RI_STAT Field Descriptions Bit Field Description 31 1 Reserved Reserved 0 RI_STARTED Ri check started status This signal is used for h...

Page 748: ...haking 0 Disable 1 Enable 6 3 2 21 Ri Line Start Register RI_START The Ri line start register is shown in Figure 6 43 and described in Table 6 52 Figure 6 43 Ri Line Start Register RI_START 31 8 7 0 R...

Page 749: ...described in Table 6 54 Figure 6 45 Ri From RX Registers High RI_RX_H 31 8 7 0 Reserved RI_RX R 0h R 0h LEGEND R W Read Write R Read only n value after reset Table 6 54 Ri From RX Registers High RI_RX...

Page 750: ...O DE Delay Register DE_DLY 31 8 7 0 Reserved DE_DLY R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 56 VIDEO DE Delay Register DE_DLY Field Descriptions Bit Field Description...

Page 751: ...ositive polarity leading edge rises 1 Negative polarity leading edge falls Set this bit to the input HSYNC polarity for the source that provides HSYNC For embedded syncs set this bit to the desired HS...

Page 752: ...VIDEO DE Count Register DE_CNTL Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 DE_CNT Defines the width of the active display The unit of measure is pixels This register should be...

Page 753: ...ght of the active display The unit of measure is lines HSYNC pulses Set this register to the desired vertical resolution For interlaced modes set this register to the number of lines per field which i...

Page 754: ...d Write R Read only n value after reset Table 6 63 Video H Resolution Register HRES_L Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 H_RES Measures the time between two HSYNC acti...

Page 755: ...ad Write R Read only n value after reset Table 6 65 Video V Resolution Low Register VRES_L Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 V_RES Measures the time between two VSYNC...

Page 756: ...this bit enables detection circuits to locate the position of VSYNC relative to HSYNC and only include HSYNC edges that are greater than 3 4 lines from VSYNC in the line count for DE_TOP Enable Vsync...

Page 757: ...ing edge falls 0 HPOL_DET Detected input HSYNC polarity using internal circuit 0 Active high leading edge rises 1 Active low leading edge falls 6 3 2 38 Video Hbit to HSYNC Register HBIT_2HSYNC1 The v...

Page 758: ...d Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 HBIT_TO_HSYNC Creates HSYNC pulses Set this register to the delay from the detection of an EAV sequence H bit change from 1 to 0 to the...

Page 759: ...after reset The video field2 HSYNC offset register is shown in Figure 6 63 and described in Table 6 72 Table 6 72 Video Field2 HSYNC Offset Register FLD2_HS_OFSTH Field Descriptions Bit Field Descript...

Page 760: ...d Write R Read only n value after reset Table 6 74 Video HSYNC Length Register HWIDTH2 Field Descriptions Bit Field Description 31 2 Reserved Reserved 1 0 HWIDTH Sets the width of the HSYNC pulses Set...

Page 761: ...ength register is shown in Figure 6 67 and described in Table 6 76 Figure 6 67 Video VSYNC Length Register VWIDTH 31 6 5 0 Reserved VWIDTH R 0h R W 0h LEGEND R W Read Write R Read only n value after r...

Page 762: ...odes 1 All 12 bit 4 2 2 input modes For 4 2 2 inputs wider than 8 bits but less than 12 bits the unused bits should be cleared to 0 4 CSCSEL Color space conversion standard select 0 BT 601 conversion...

Page 763: ...nput video channel 0b00 8 bits per channel or 24 bit bus mode 0b01 10 bits per channel or 30 bit bus mode 0b10 12 bits per channel or 36 bit bus mode 0b11 Reserved 5 Reserved 0 Reserved 4 CLIP_CS_ID I...

Page 764: ...led 1 Enabled When this bit is set the HDMI transmitter expands the range of pixel data values from 16 235 into the full 8 bit range of 0 255 This is suitable for translating input YCbCr data into out...

Page 765: ...Read only n value after reset Table 6 81 Video Blanking Register VID_BLANK2 Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 VID_BLANK2 Defines the video blanking value for Channel...

Page 766: ...et Table 6 83 Deep Color Header Register DC_HEADER Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 DC_HEADER This is the least siginificant byte of the deep color header that sends...

Page 767: ...ion 1 Enable the function 4 422_EN Enable Mode 4 2 2 for dithering and clipping 0 Disable the function 1 Enable the function 3 D_BC_EN Enable adding random number on Blue channel data 0 Disable the fu...

Page 768: ...CT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 XV_CO_OV Override internal CSC coefficients with register 51 to XX values 0 Disable the function 1 Enable the function 1 XV...

Page 769: ...COEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 87 RGB_2_xvYCC Conversion R_2_Y Register R2Y_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserved...

Page 770: ...COEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 89 RGB_2_xvYCC Conversion G_2_Y Register G2Y_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserved...

Page 771: ..._H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 91 RGB_2_xvYCC Conversion B_2_Y Register B2Y_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 B...

Page 772: ...BCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 93 RGB_2_xvYCC Conversion R_2_Cb Register R2CB_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserv...

Page 773: ...BCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 95 RGB_2_xvYCC Conversion G_2_Cb Register G2CB_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserv...

Page 774: ...BCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 97 RGB_2_xvYCC Conversion B_2_Cb Register B2CB_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserv...

Page 775: ...COEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 99 RGB_2_xvYCC Conversion R_2_Cr Register R2CR_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reserve...

Page 776: ...RCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 101 RGB_2_xvYCC Conversion G_2_Cr Register G2CR_COEFF_UP Field Descriptions Bit Field Description 31 8 Reserved Reser...

Page 777: ...0 Reserved B2CRCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 103 RGB_2_xvYCC Conversion B_2_Cr Register B2CR_COEFF_UP Field Descriptions Bit Field Description 31 8...

Page 778: ...eserved RGB_OFFS_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 105 RGB_2_xvYCC RGB Input Offset Register RGB_OFFSET_UP Field Descriptions Bit Field Description 31 8 Reser...

Page 779: ...nversion Y Output Offset Register Y_OFFSET_UP 31 7 6 0 Reserved Y_OFFS_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 107 RGB_2_xvYCC Conversion Y Output Offset Register Y...

Page 780: ...wn in Figure 6 100 and described in Table 6 109 Figure 6 100 RGB_2_xvYCC Conversion CbCr Output Offset Register CBCR_OFFSET_UP 31 7 6 0 Reserved CBCR_OFFS_H R 0h R W 0h LEGEND R W Read Write R Read on...

Page 781: ...interrupt asserted if hot plug detect has changed state The HDMI transmitter signals a change in the connectivity to a Sink either unplug or plug HDMI specifies that hot plug be active only when the S...

Page 782: ...rflows when more samples are written into it than are drawn out across the HDMI link Such a condition can occur from a transient change in the Fs or pixel clock rate 0 UNDER_RUN Audio FIFO underflow S...

Page 783: ...ge in ACR CTS value This interrupt occurs when the change is of an unexpected magnitude Such an interrupt should be expected when changing Fs or pixel clock frequency 2 ACR_OVR ACR packet overwrite Th...

Page 784: ...ICNT 5 RI_ERR_1 Ri did not change between frame 127 and 0 4 RI_ERR_0 Ri not read within one frame 3 DDC_CMD_DONE DDC command is complete 2 DDC_FIFO_HALF DDC FIFO is half full 1 DDC_FIFO_FULL DDC FIFO...

Page 785: ...to clear the bit and the interrupt 1 Interrupt asserted 1 REG_INTR4_STAT1 For each interrupt bit 0 No interrupt occurred Write any bit to 1 to clear the bit and the interrupt 1 Interrupt asserted 0 DS...

Page 786: ...f the HDMI transmitter detects an 8 bit preamble in the S PDIF input stream before the subframe has been captured this interrupt is set A S PDIF input that stops signaling or a flat line condition can...

Page 787: ...Change in ACR CTS value This interrupt occurs when the change is of an unexpected magnitude Such an interrupt should be expected when changing Fs or pixel clock frequency 2 ACR_OVR ACR packet overwri...

Page 788: ...e 0 ICNT 5 RI_ERR_1 Ri did not change between frame 127 and 0 4 RI_ERR_0 Ri not read within one frame 3 DDC_CMD_DONE DDC command is complete 2 DDC_FIFO_HALF DDC FIFO is half full 1 DDC_FIFO_FULL DDC F...

Page 789: ...interrupt occurred Write any bit to 1 to clear the bit and the interrupt 1 Interrupt asserted 1 REG_INTR4_STAT1 For each interrupt bit 0 No interrupt occurred Write any bit to 1 to clear the bit and...

Page 790: ...R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 120 xvYCC_2_RGB Control Register XVYCC2RGB_CTL Field Descriptions Bit Field Description 31 5 Reserved...

Page 791: ...FF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 122 xvYCC_2_RGB Conversion Y_2_R Register Y2R_COEFF_UP Field Descriptions Bit Field Description 31 5 Reserved Reserved 4...

Page 792: ...CR2RCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 124 xvYCC_2_RGB Conversion Cr_2_R Register C2R2R_COEFF_UP Field Descriptions Bit Field Description 31 5 Reserved R...

Page 793: ...31 5 4 0 Reserved CB2BCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 126 xvYCC_2_RGB Conversion Cb_2_B Register CB2B_COEFF_UP Field Descriptions Bit Field Descripti...

Page 794: ...R2GCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 128 xvYCC_2_RGB Conversion Cr_2_G Register CR2G_COEFF_UP Field Descriptions Bit Field Description 31 5 Reserved Res...

Page 795: ...B2GCOEFF_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 130 xvYCC_2_RGB Conversion Cb_2_G Register CB2G_COEFF_UP Field Descriptions Bit Field Description 31 5 Reserved Res...

Page 796: ...0 Reserved YOFFS1_H R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 132 xvYCC_2_RGB Conversion Y Offset Register YOFFSET1_UP Field Descriptions Bit Field Description 31 4 Res...

Page 797: ...GB Conversion Offset1 Register OFFSET1_MID 31 8 7 0 Reserved OFFS1_M R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 134 xvYCC_2_RGB Conversion Offset1 Register OFFSET1_MID F...

Page 798: ...Write R Read only n value after reset Table 6 136 xvYCC_2_RGB Conversion Offset2 Register OFFSET2_LOW Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 OFFS2_L xvYCC2RGB offset2 coe...

Page 799: ...served DC_LEV_L R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 138 xvYCC_2_RGB Conversion DC Level Register DCLEVEL_LOW Field Descriptions Bit Field Description 31 8 Reserve...

Page 800: ...d Write R Read only n value after reset Table 6 140 DDC I2C Manual Register DDC_MAN Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 MAN_OVR Manual override of SCL and SDA out...

Page 801: ...DDC I2C Target Segment Address Register DDC_SEGM 31 8 7 0 Reserved DDC_SEGM R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 142 DDC I2C Target Segment Address Register DDC_SE...

Page 802: ...ue after reset Table 6 144 DDC I2C Data Count Register DDC_COUNT1 Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 DDC_COUNT The total number of bytes to be read from the slave or w...

Page 803: ...ister DDC_STATUS is shown in Figure 6 137 and described in Table 6 146 Figure 6 137 DDC I2C Status Register DDC_STATUS 31 16 Reserved R 0h 15 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved BUS_LOW NO_ACK IN...

Page 804: ...led 3 0 DDC_CMD 0 DDC command 0b1111 Abort transaction 0b1001 Clear FIFO 0b1010 Clock SCL 0b0000 Current address read with no ACK on last byte 0b0010 Sequential read with no ACK on last byte 0b0100 En...

Page 805: ...DDC I2C FIFO Count Register DDC_FIFOCNT 31 5 4 0 Reserved DDC_FIFOCNT R 0h R 0h LEGEND R W Read Write R Read only n value after reset Table 6 149 DDC I2C FIFO Count Register DDC_FIFOCNT Field Descript...

Page 806: ...Reserved 0 Reserved 1 CRC_ERR 1 CRC error 0 CMDD 1 Command done last operation completed successfully 0 After reset 1 Once the KSV keys are read when osclk is running 6 3 2 120 ROM Command Register E...

Page 807: ...RC to verify OTP contents 0 0b1000 Run only BIST self authentication test 2 2 pass authentication to verify the HDCP cipher engine 0 All other values are reserved Before writing a new value into this...

Page 808: ...1 Field Descriptions Bit Field Description 31 8 Reserved Reserved 7 0 HEADER1 Gamut metadata header information 6 3 3 2 Gamut Metadata Register GAMUT_HEADER2 The gamut metadata register is shown in Fi...

Page 809: ...e Description 6 4 GBD_PROFILE Transmission profile number Values from 4h 7h are reserved 0 P0 1h P1 2h P2 3h P3 3 0 AFF_GAM_SEQ_NUM Indicates which video fields are relevant for this metadata 809 SPRU...

Page 810: ...erved 0 Reserved 5 4 PACKET_SEQ Indicates the position of current packet 0 Intermediate packet 1h First packet 2h Last packet 3h Only packet in sequence 3 0 CUR_GAM_SEQ_NUM Indicates the gamut number...

Page 811: ...s 80h I2S_CHST2 Audio In I2S Channel Status Registers 84h I2S_CHST4 Audio In I2S Channel Status Registers 88h I2S_CHST5 Audio In I2S Channel Status Registers 8Ch ASRC Audio Sample Rate Conversion Regi...

Page 812: ...Register 6 3 4 1 ACR Control Register ACR_CTRL Figure 6 147 ACR Control Register ACR_CTRL 31 16 Reserved R 0h 15 2 1 0 Reserved NCTSPKT_EN CTS_SEL R 0h R W R W LEGEND R W Read Write R Read only n valu...

Page 813: ...de 0b000 MCLK is 128 Fs 0b001 MCLK is 256 Fs 0b010 MCLK is 384 Fs 0b011 MCLK is 512 Fs 0b100 MCLK is 768 Fs 0b101 MCLK is 1024 Fs 0b110 MCLK is 1152 Fs 0b111 MCLK is 192 Fs The HDMI transmitter uses t...

Page 814: ...6 150 ACR N Software Value Register N_SVAL2 31 8 7 0 Reserved N_SVAL2 R 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 6 161 ACR N Software Value Register N_SVAL2 Field Descrip...

Page 815: ...1 8 Reserved 0 Reserved RO 7 0 CTS_SVAL 0 CTS Value for audio clock regeneration method a 20 bit value Diagnostic R W use and applied only when the CTS_SEL bit in register ACR_CTRL is set to 1 815 SPR...

Page 816: ...CTS_SEL bit in register ACR_CTRL is set to 1 6 3 4 9 CTS_HVAL1 Table 6 166 CTS_HVAL1 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 CTS_HVAL 0 CTS Value for audio...

Page 817: ...d 0 Reserved RO 7 SD3_EN I2S input channel 3 R W 0 Disable 1 Enable 6 SD2_EN I2S input channel 2 R W 0 Disable 1 Enable 5 SD1_EN I2S input channel 1 R W 0 Disable 1 Enable 4 SD0_EN I2S input channel 0...

Page 818: ...FS Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 5 HW_SPDIF_ 0 Channel status bits 33 to 35 bit 33 LSB Combines with HW_MAXLEN to RO LEN indicate sample size Bits M...

Page 819: ...e frame is marked as invalid if the R W HRESH number of bi phase mark encoding errors in the audio stream exceeds this threshold level during frame decoding 6 3 4 17 I2S_IN_MAP Table 6 174 I2S_IN_MAP...

Page 820: ...bit value R W 0 PCM 1 Compressed 3 I2S_WS WS polarity R W 0 Left polarity when WS is LOW 1 Left polarity when WS is HIGH 2 I2S_JUST SD justify R W 0 Data is left justified 1 Data is right justified 1...

Page 821: ...S_CHST4 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 4 CLK_ACCUR 0 Clock Accuracy R W 3 0 SW_SPDIF_ Fh Sampling frequency as set by software R W FS 6 3 4 24 I2S_CH...

Page 822: ...en SRC_EN is set to 1 0 SRC_EN Audio sample rate conversion 0 Disabled 1 Enabled 6 3 4 26 I2S_IN_LEN Table 6 183 I2S_IN_LEN Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved...

Page 823: ...on in the packet to the HDMI Receiver 5 3 PACKET_M 0 Specifies the number of bits per pixel sent to the paketizer R W ODE 0b000 Reserved 0b001 Reserved 0b010 Reserved 0b011 Reserved 0b100 24 bits per...

Page 824: ...ype 31 3 Reserved 0 Reserved RO 2 MUTE General Control Packet mute status R W 0 No packet with SETAVM 1 has been sent 1 A packet with SETAVM 1 has been sent 1 NPACKET_E 0 Enables null packet flooding...

Page 825: ...Description Type 31 8 Reserved 0 Reserved RO 7 VID_BYP_E Enable bypath of the video path The CORE_ISO_EN bit in register R W N TEST_TXCTRL must be set and the HDCP cypher must be disabled HDCP_CTRL EW...

Page 826: ...nfoFrame transmission R W 0 Disabled send once after enable bit is set 1 Enabled send in every VBLANK period 3 SPD_EN Enable General Control Packet transmission R W 0 Disabled 1 Enabled 2 SPD_RPT Repe...

Page 827: ...Repeat Generic 2 Packet transmission R W 0 Disabled send once after enable bit is set 1 Enabled send in every VBLANK period 3 CP_EN Enable General Control Packet transmission R W 0 Disabled 1 Enabled...

Page 828: ..._VERS 0 AVI InfoFrame Version Code AVI_HDR 15 8 R W 6 3 4 38 AVI_LEN Table 6 195 AVI_LEN Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 AVI_LEN 0 AVI InfoFrame Len...

Page 829: ...ved RO 7 0 SPD_TYPE 0 SPD InfoFrame Type Code SPD_HDR 7 0 R W 6 3 4 42 SPD_VERS Table 6 199 SPD_VERS Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 SPD_VERS 0 SPD...

Page 830: ...rved RO 7 0 SPD_DATA 0 SPD InfoFrame Data Bytes R W 6 3 4 46 AUDIO_TYPE Table 6 203 AUDIO_TYPE Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 AUDIO_TYP 0 AUDIO Inf...

Page 831: ...oFrame Checksum AUDIO_HDR 31 24 R W UM 6 3 4 50 AUDIO_DBYTE__0 AUDIO_DBYTE__9 Table 6 207 AUDIO_DBYTE__0 AUDIO_DBYTE__9 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO...

Page 832: ...rame Length MPEG_HDR 23 16 R W 6 3 4 54 MPEG_CHSUM Table 6 211 MPEG_CHSUM Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 MPEG_CHS 0 MPEG InfoFrame Checksum MPEG_HD...

Page 833: ...be incorrect The HDMI Transmitter sends blanklevel data for all video packets and 00 for all audio packet data When the AVMUTE flag is set the Sink assumes that no valid data is being received Option...

Page 834: ...5_8 CEC Capture ID0 Register 90h CEC_INT_ENABLE_0 CEC Interrupt Enable Register0 94h CEC_INT_ENABLE_1 CEC Interrupt Enable Register1 98h CEC_INT_STATUS_0 CEC Interrupt Status Register0 9Ch CEC_INT_STA...

Page 835: ...3 0 FW_REV_ID 4h Firmware Revision ID RO 6 3 5 5 CEC_DBG_0 Table 6 222 CEC_DBG_0 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 STB_LOW_P 0 Start Bit Low Period Me...

Page 836: ...0 No 1 Yes self resetting bit 6 4 FR_RT_CNT 0 Frame Retransmit Count Values 0 to 5 RO 3 Reserved 0 Reserved RO 2 INV_ACK Invert ACK to Broadcast Commands R W 0 No 1 Yes 1 ACKN_HEAD ACK NACK Header Bl...

Page 837: ...ed 0 Reserved RO 2 CEC_FORCE_NON_CALIB 1 Must be set to 1 if calibration is not needed If a 2 MHz christal clock is R W available 1 CEC_CAL_EN 0 CEC calibration enable register self clearing R W 0 CEC...

Page 838: ...RO 7 0 CEC_CAP_ID 0 The CEC Capture ID register is separate from the CEC Initiator ID It selects the received R W commands that will be captured in the receive FIFO and acknowledged If the command des...

Page 839: ...CEC_INTR1_MASK0 Command Being Received Event R W 0 Disable 1 Enable 6 3 5 18 CEC_INIT_ENABLE_1 Table 6 235 CEC_INIT_ENABLE_1 Field Descriptions Bit Field Value Description Type 31 4 Reserved 0 Reserve...

Page 840: ...FIFO Not Empty Event Pending R W 0 Disable 1 Enable 0 CEC_INTR1_STAT0 Command Being Received Event Pending R W 0 Disable 1 Enable 6 3 5 20 CEC_INIT_STATUS1 Table 6 237 CEC_INIT_STATUS1 Field Descripti...

Page 841: ...ns the number of frames awaiting reading RO in the FIFO 0 3 3 0 CEC_RX_BYTE_CNT 0 CEC Receive Byte Count returns the number of operands in the current frame RO 6 3 5 23 CEC_RX_CMD_HEADER Table 6 240 C...

Page 842: ...42 CEC_RX_OPERAND__0 CEC_RX_OPERAND__14 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 0 CEC_RX_OP 0 CEC Rx Operand R W 842 High Definition Multimedia Interface HDMI...

Page 843: ...ut 0 When receiver is disconnected 1 When receiver is connected R 6 3 6 2 TMDS_CNTL3 Table 6 245 TMDS_CNTL3 Field Descriptions Bit Field Value Description Type 31 5 Reserved 5h Reserved RO 4 3 clkmult...

Page 844: ...ncoder R W 1 Bypass the DVI encoder 1 0 Reserved 0 Reserved RO 6 3 6 4 TMDS_CNTL9 Table 6 247 TMDS_CNTL9 Field Descriptions Bit Field Value Description Type 31 8 Reserved 0 Reserved RO 7 ten_bit_bypas...

Page 845: ...ny I2C bus compatible device that connects via the I2C serial bus External components attached to the I2C bus can serially transmit receive up to 8 bit data to from the CPU device through the two wire...

Page 846: ...bus can also be considered as master or slave when performing data transfers Note that a master device is the device which initiates a data transfer on the bus and generates the clock signals to perm...

Page 847: ...pheral A noise filter on each of the two pins I2C_SDA and I2C_SCL An arbitrator to handle arbitration between the I2C peripheral when it is a master and another master Interrupt generation logic so th...

Page 848: ...are reset to power up reset values The I2C_EN bit in the I2C_CON register can be used to hold the I2C module in reset When the system bus reset is removed PIRSTNA 1 I2C_EN 0 keeps the functional part...

Page 849: ...ber of bytes that can be transmitted or received is restricted by the value programmed in the DCOUNT register The data is transferred with the most significant bit MSB first Each byte is followed by a...

Page 850: ...ster receiver is entered after the slave address byte and bit R W_ has been transmitted if R W_ is high Serial data bits received on bus line SDA are shifted in synch with the self generated clock pul...

Page 851: ...ions only one master device generates the clock signal SCL During the arbitration procedure however there are two or more master devices and the clock must be synchronized so that the data output can...

Page 852: ...after the module being in idle mode have detected synchronously or asynchronously a possible Start Condition on the bus signalized with WakeUp Access Error interrupt AERR is generated if a Data read...

Page 853: ...h of the FIFOs can be configured at integration via a generic parameter which will also be reflected in I2C_IRQSTATUS_RAW FIFODEPTH register 7 2 13 1 FIFO Interrupt Mode Operation In FIFO interrupt mo...

Page 854: ...t the interrupt until the interrupt condition is not met When detecting an interrupt request XRDY or RRDY type the CPU can be programmed to write read the amount of data bytes specified by the corresp...

Page 855: ...R field Figure 7 11 Receive FIFO DMA Request Generation In transmit mode a DMA request is automatically asserted when the transmit FIFO is empty This request should be de asserted when the number of b...

Page 856: ...cordingly DMA requests will be generated for each byte requested by the remote I2C master to be transferred over the I2C bus This configuration will prevent the I2C core to request additional data fro...

Page 857: ...RSH the transmit draining interrupt I2C_IRQSTATUS_RAW XDR will be asserted to inform the local host that it can read the amount of data remained to be written in the TX FIFO I2C_BUFSTAT TXSTAT The CPU...

Page 858: ...setting or testing individually bit fields within a register Table 7 3 I2C Registers Address Offset Acronym Register Name Section 00h I2C_REVNB_LO Module Revision Register LOW BYTES Section 7 3 1 04h...

Page 859: ...pt vector register I2C_IV is revision 1 x I2C controller with interrupt using status register bits I2C_IRQSTATUS_RAW is revision 2 x Figure 7 14 Module Revision Register LOW BYTES I2C_REVNB_LO 31 16 R...

Page 860: ...value after reset Table 7 5 Module Revision Register HIGH BYTES I2C_REVNB_HI Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 14 SCHEME 0 3h Used to distinguish between old...

Page 861: ...this case the first transfer will not be taken into account by the module NACK will be detected by the external master 7 5 Reserved 0 Reads return 0h 4 3 IDLEMODE Idle Mode selection bits These two b...

Page 862: ...iptions Bit Field Value Description 31 15 Reserved 0 Write 0s for future compatibility Read returns 0 14 XDR Transmit draining IRQ status I2C Master Transmit mode only This read clear only bit is set...

Page 863: ...art condition MST TRX and STT must be set to 1 in the I2C_CON register To end a transmission with a stop condition STP must be set to 1 in the I2C_CON register When BB 1 and STT 1 a restart condition...

Page 864: ...a read access will return to the previous read data value When the TX FIFO is full a write access is ignored In both events the FIFO pointers will not be updated When this bit is set to 1 by the core...

Page 865: ...h acknowledge received from the master if TXTRSH 1 When this bit is set to 1 by the core an interrupt is signaled to the local host if the interrupt was enabled The CPU can also poll this bit refer to...

Page 866: ...e has been received When a NACK event occurs on the bus this bit is set to 1 the core automatically ends the transfer and clears the MST STP bits in the I2C_CON register and the I2C becomes a slave Cl...

Page 867: ...e after reset Table 7 9 I2C Status Register I2C_IRQSTATUS Field Descriptions Bit Field Value Description 31 15 Reserved 0 Write 0s for future compatibility Read returns 0 14 XDR Transmit draining IRQ...

Page 868: ...naled to MPUSS Write 1 to clear 0 No data available 1 Receive data available 2 ARDY Register access ready IRQ enabled status When set to 1 it indicates that previous access has been performed and regi...

Page 869: ...rupt disabled 1 Transmit draining interrupt enabled 13 RDR_IE Receive draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT RDR 0 Receive draining interrupt disabled 1...

Page 870: ...bit in I2C_STAT RRDY 0 Receive data ready interrupt disabled 1 Receive data ready interrupt enabled 2 ARDY_IE Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit i...

Page 871: ...1 Transmit draining interrupt enabled 13 RDR_IE Receive draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT RDR 0 Receive draining interrupt disabled 1 Receive dra...

Page 872: ...bit in I2C_STAT RRDY 0 Receive data ready interrupt disabled 1 Receive data ready interrupt enabled 2 ARDY_IE Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit...

Page 873: ...Enable Register I2C_WE Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 XDR_WE Transmit draining wakeup enable This read write bit is used to enable or disable wakeup signa...

Page 874: ...bled 5 GC_WE General call IRQ wakeup enable This read write bit is used to enable or disable wakeup signal generation when I2C module is in idle mode and a general call is received on I2C line 0 Gener...

Page 875: ...STT is enabled and the module enters in Idle Mode If the module loses the arbitration an Arbitration Lost event is raised and the module needs to inform CPU about transmission error Note The AL wakeu...

Page 876: ...ABLE_SET 0 1 Receive DMA channel enable set 7 3 11 Transmit DMA Enable Set Register I2C_DMATXENABLE_SET The 1 bit field enables a transmit DMA request Writing a 1 to this field will set it to 1 Writin...

Page 877: ...LE_CLEAR 0 1 Receive DMA channel enable clear 7 3 13 Transmit DMA Enable Clear Register I2C_DMATXENABLE_CLR The 1 bit field disables a transmit DMA request Writing a 1 to a bit will clear it to 0 Anot...

Page 878: ...terrupt enabled 13 RDR Receive draining wakeup set 0 Receive draining interrupt disabled 1 Receive draining interrupt enabled 12 Reserved 0 Reserved 11 ROVR Receive overrun wakeup set 0 Receive overru...

Page 879: ...ady wakeup disabled 1 Register access ready wakeup enabled 1 NACK No acknowledgment IRQ wakeup set 0 Not Acknowledge wakeup disabled 1 Not Acknowledge wakeup enabled 0 AL Arbitration lost IRQ wakeup s...

Page 880: ...nterrupt enabled 13 RDR Receive draining wakeup set 0 Receive draining interrupt disabled 1 Receive draining interrupt enabled 12 Reserved 0 Reserved 11 ROVR Receive overrun wakeup set 0 Receive overr...

Page 881: ...ady wakeup disabled 1 Register access ready wakeup enabled 1 NACK No acknowledgment IRQ wakeup set 0 Not Acknowledge wakeup disabled 1 Not Acknowledge wakeup enabled 0 AL Arbitration lost IRQ wakeup s...

Page 882: ...FO Management subsection Figure 7 30 Buffer Configuration Register I2C_BUF 31 16 Reserved R 0 15 14 13 8 7 6 5 0 RDMA_EN RXFIFO_CLR RXTRSH XDMA_EN TXFIFO_CLR TXTRSH R W 0 R W 0 R W 0 R W 0 R W 0 R W 0...

Page 883: ...data ready status I2C_IRQSTATUS_RAW XRDY bit is forced to 0 by the core 0 Transmit DMA channel disabled 1 Transmit DMA channel enabled Value after reset is low 6 TXFIFO_CLR Transmit FIFO clear When se...

Page 884: ...itial value only before a start condition and after a stop condition When DCOUNT reaches 0 the core generates a stop condition if a stop condition was specified I2C_CON STP 1 and the ARDY status flag...

Page 885: ...ndpoint When read this register contains the received I2C data When written this register contains the byte value to transmit over the I2C data In SYSTEST loop back mode I2C_SYSTEST TMODE 11 this regi...

Page 886: ...d can be accessed The CPU must set this bit to 1 for normal operation 0 Controller in reset FIFO are cleared and status bits are set to their default value 1 Module enabled Value after reset is low 14...

Page 887: ...6 XOA1 Expand own address 1 I2C mode only When set this bit expands the first alternative own address OA1 to 10 bit 0 7 bit address mode 1 10 bit address mode Value after reset is low 5 XOA2 Expand o...

Page 888: ...n STT has been set to 1 and receiving of ARDY no modification must be done in this register Changing it may result in an unpredictable behavior This register is used to specify the module s base I2C 7...

Page 889: ...D R W Read Write R Read only n value after reset Table 7 25 I2C Slave Address Register I2C_SA Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 SA 0 3FFh Slave address This...

Page 890: ...e 7 26 I2C Clock Prescaler Register I2C_PSC Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 PSC 0 FFh Fast Standard mode prescale sampling clock divider value The core uses...

Page 891: ...period Value after reset is low all 8 bits 7 3 25 I2C SCL High Time Register I2C_SCLH CAUTION During an active mode I2C_EN bit in I2C_CON register is set to 1 no modification must be done in this reg...

Page 892: ...e after reset is low 14 FREE Free running mode on breakpoint This bit is used to determine the state of the I2C controller when a breakpoint is encountered in the HLL debugger Note This bit can be set...

Page 893: ...ior attempting to clear a status bit 0 No action 1 Set all interrupt status bits to 1 Value after reset is low 10 9 Reserved 0 Reserved 8 SCL_I_FUNC SCL line input value functional mode This read only...

Page 894: ...alue In normal functional mode ST_EN 0 this read only bit always reads 0 In system test mode ST_EN 1 TMODE 11 this read only bit returns the logical state taken by the SDA line either 1 or 0 Read 0 Re...

Page 895: ...s FIFO 2h 32 bytes FIFO 3h 64 bytes FIFO Value after reset is given by the boundary module generic parameter 13 8 RXSTAT 0 3Fh RX buffer status This read only field indicates the number of bytes to be...

Page 896: ...d Write R Read only n value after reset Table 7 31 Own Address 1 OA1 I2C_OA1 Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 OA1 0 3FFh Own address 1 This field specifies...

Page 897: ...Read Write R Read only n value after reset Table 7 32 I2C Own Address 2 Register I2C_OA2 Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 OA2 0 3FFh Own address 2 This fie...

Page 898: ...Read Write R Read only n value after reset Table 7 33 I2C Own Address 3 Register I2C_OA3 Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 OA3 0 3FFh Own address 2 This fie...

Page 899: ...own address addressed the module 0 Own address inactive 1 Own address active Value after reset is low 2 OA2_ACT Own address 2 active When a bit location is set to 1 by the core it signalizes to the L...

Page 900: ...et is low 2 OA2_EN Enable I2C clock blocking for own address 2 When the CPU sets a bit location to 1 if an external master using the corresponding own address addresses the core the core will block th...

Page 901: ...This chapter discusses the interrupt controller Topic Page 8 1 Introduction 902 8 2 Architecture 905 8 3 Basic Programming Model 908 8 4 Registers 917 901 SPRUGX9 15 April 2011 Interrupt Controller S...

Page 902: ...Each interrupt can be steered to nFIQ or nIRQ Independent priority sorting for nFIQ and nIRQ Figure 8 1 shows the internal interrupt scheme Figure 8 1 Interrupt Controller 8 1 2 Functional Block Diagr...

Page 903: ...Priority Threshold ITRp Interrupt Input Status SIR_FIQ Active Interrupt Nb Spurious Flag and Priority FIQ_PRIORITY SIR_IRQ IRQ_PRIORITY Priority Sorting IRQ Priority Sorter FIQ Priority Sorter IRQ In...

Page 904: ...ncoming interrupts and the two interrupt inputs of the ARM A8 The two interrupts inputs to ARM are FIQ and IRQ Figure 8 3 shows the integration of the interrupt controller in the ARM A8 subsystem The...

Page 905: ...nsure that interrupts of unavailable modules and features are masked in ARM A8 subsystem Table 8 2 Interrupt Controller Interrupt Inputs and Outputs Type Number Name Mapping Comment Interrupt request...

Page 906: ...value is also the reset default for backward compatibility with previous versions of the INTC 8 2 3 3 Priority Sorting A priority level 0 being the highest is assigned to each incoming interrupt line...

Page 907: ...e can be enabled dynamically according to the requirements of the device After reset this mode is disabled by default 8 2 5 Error Handling The following accesses will cause error Privilege violation a...

Page 908: ...FIQ sequence are shown after a character in the code below 1 One or more unmasked incoming interrupts M_IRQ_n signals are received and IRQ or FIQ outputs IRQ FIQ are not currently asserted 2 If the IN...

Page 909: ...LDR R10 R10 Get the INTCPS_SIR_IRQ INTCPS_SIR_FIQ register AND R10 R10 ACTIVEIRQ_MASK Apply the mask to get the active IRQ number Jump to relevant subroutine handler LDR PC PC R10 lsl 2 PC base addres...

Page 910: ...egister is a write only register so no need to write back others bits MOV R0 NEWIRQAGR_MASK NEWFIQAGR_MASK Get the NEWIRQAGR NEWFIQAGR bit position LDR R1 INTCPS_CONTROL_ADDR STR R0 R1 Write the NEWIR...

Page 911: ...n number N ISR in IRQ FIQ Mode Step 5 Save ARM critical context Identify interrupt source Branch to relevant interrupt subroutine handler Relevant Subroutine Handler in IRQ FIQ Mode Step 6 Handles the...

Page 912: ...text registers 2 Save the INTCPS_THRESHOLD PRIORITYTHRESHOLD field before modifying it 3 Read the active interrupt priority in the INTCPS_IRQ_PRIORITY IRQPRIORITY INTCPS_FIQ_PRIORITY FIQPRIORITY field...

Page 913: ...ource of the IRQ remains active and it is finally processed when the priority threshold falls to a priority sufficiently low to allow it to be processed The precaution of writing to New FIQ Agreement...

Page 914: ...ironment IRQ_ISR_end Step 1 Read modify write the CPSR to disable IRQs FIQs at ARM side MRS R0 CPSR Read the CPSR ORR R0 R0 0x80 0x40 Set the I F bit MSR CPSR R0 Write it back to disable IRQs Step 2 R...

Page 915: ...ld Get active IRQ priority Set the IRQ priority to priority threshold Identify interrupt source Allow a new IRQ and FIQ at INTC side by setting the NEWIRQAGR and NEWFIQAGR bits to 1 Enable IRQ FIQ at...

Page 916: ...ugh priority The precaution of writing to New FIQ Agreement as well as New IRQ Agreement is not required during an IRQ ISR as FIQ sorting will not be affected provided all FIQ priorities are higher th...

Page 917: ...gister Section 8 4 4 44h INTCPS_SIR_FIQ Spurious FIQ Flag Register Section 8 4 5 48h INTCPS_CONTROL Control Register Section 8 4 6 4Ch INTCPS_PROTECTION Protection Mode Register Section 8 4 7 50h INTC...

Page 918: ...NFIG Register 31 16 Reserved R 0 15 2 1 0 Reserved SOFTRESET AUTOIDLE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 5 INTCPS_SYSCONFIG Register Field Descriptions Bit F...

Page 919: ...t monitoring 0 Internal module reset is ongoing 1 Reset complete 8 4 4 INTCPS_SIR_IRQ Register This register supplies the currently active IRQ interrupt number Figure 8 9 INTCPS_SIR_IRQ Register 31 16...

Page 920: ...r This register contains the new interrupt agreement bits Figure 8 11 INTCPS_CONTROL Register 31 16 Reserved R 0 15 2 1 0 Reserved NEWFIQAGR NEWIRQAGR R 0 W 0 W 0 LEGEND R W Read Write R Read only n v...

Page 921: ...ccessible only in privileged mode 8 4 8 INTCPS_IDLE Register This register controls the functional clock auto idle and the synchronizer clock auto gating Figure 8 13 INTCPS_IDLE Register 31 16 Reserve...

Page 922: ...purious IRQ flag 6 0 IRQPRIORITY 0 7Fh Current IRQ priority 8 4 10 INTCPS_FIQ_PRIORITY Register This register supplies the currently active FIQ priority level Figure 8 15 INTCPS_FIQ_PRIORITY Register...

Page 923: ...ture compatibility Read returns reset value 7 0 PRIORITYTHRESHOLD 0 FFh Priority threshold 0 7Fh Priority threshold FFh Priority threshold is disabled 8 4 12 INTCPS_ITR0 3 Registers This register show...

Page 924: ...ND W Write only n value after reset Table 8 17 INTCPS_MIR_CLEARn Register Field Descriptions Bit Field Value Description 31 0 MIRCLEAR n Clear the interrupt mask n bits Read returns 0 W0 No effect W1...

Page 925: ...r the software interrupt bits Figure 8 22 INTCPS_ISR_CLEARn Register 31 0 ISRCLEAR n R W FFFF FFFFh LEGEND R Read only n value after reset Table 8 20 INTCPS_ISR_CLEARn Register Field Descriptions Bit...

Page 926: ...FIQ IRQ steering Figure 8 25 INTCPS_ILRm Register 31 16 Reserved R 0 15 9 8 2 1 0 Reserved PRIORITY Reserved FIQNIRQ R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 2...

Page 927: ...es the secure digital secure digital I O SD SDIO card interface Topic Page 9 1 Introduction 928 9 2 Architecture 929 9 3 Low Level Programming Models 957 9 4 Registers 962 927 SPRUGX9 15 April 2011 Se...

Page 928: ...er deals with SD SDIO protocol at transmission level data packing adding cyclic redundancy checks CRC start end bit and checking for syntactical correctness The application interface can send every SD...

Page 929: ...or 4 bit transfer mode specifications for SD and SDIO cards 3 3v cards Built in 1024 byte buffer for read or write 32 bit wide access bus to maximize bus throughput Single interrupt line for multiple...

Page 930: ...DWP This input pin is used for the SD SDIO card s write protect This signal is received from a mechanical protect switch on the slot system dependant Applicable only for SD and SDIO cards that have a...

Page 931: ...ase of transmission error occurring on any of the active data lines the card sends a negative CRC status on SD_DAT0 In the case of successful transmission over all active data lines the card sends a p...

Page 932: ...se types see the SD Memory Card Specification or the SDIO Card Specification Table 9 2 Response Type Summary 1 Response Type Index Check Enable CRC Check Enable SD_CMD 17 16 SD_CMD 20 SD_CMD 19 RSP_TY...

Page 933: ...r 1 Bit Figure 9 8 Data Packet for Block Transfer 4 Bit 9 2 2 Resets 9 2 2 1 Hardware Reset The module is reinitialized by the hardware The SD_SYSSTATUS 0 RESETDONE bit can be monitored by the softwar...

Page 934: ...The SD SDIO host controller can enter into different modes and save power Normal mode Idle mode The two modes are mutually exclusive the module can be in normal mode or in idle mode The SD SDIO host c...

Page 935: ...rom the PRCM As soon as the SD SDIO controller acknowledges the idle request from the PRCM If Smart Idle modethe module does not assert any new interrupt or DMA request If Smart Idle wake up capable m...

Page 936: ...ization inside module by gating the OCP clock upon the interface activity or gating the CLKADPI clock upon the internal activity Slave Idle Modes SD_SYSCONFIG SIDLEMODE bit Force idle No idle and Smar...

Page 937: ...the service of the interrupt without updating the status SD_STAT or transmitting an interrupt request Table 9 5 lists the event flags and their mask that can cause module interrupts Table 9 5 Events...

Page 938: ...sampled during the interrupt cycle In CE ATA mode interrupt source is detected when the card drive CMD line to zero during one cycle after data transmission end SD_STAT 5 BRR SD_IE 5 IRQ Buffer Read...

Page 939: ...AT register to detect when the corresponding event occurs Writing 1 into the corresponding bit of the SD_STAT register clears the interrupt status and does not affect the interrupt line state NOTE Ple...

Page 940: ...e level when the sDMA has read one single word from the buffer Only one request is sent per block the DMA controller can make a 1 shot read access or several DMA bursts in which case the DMA controlle...

Page 941: ...buffer The block size transfer is specified in the SD_BLK 10 0 BLEN field The SDMAWREQN signal is deasserted to its inactive level when the sDMA has written one single word to the buffer Only one requ...

Page 942: ...ister is allowed only when the buffer write enable status is set to 1 SD_PSTATE 10 BWE otherwise a bad access SD_STAT 29 BADA is signaled and the data is not written The data buffer has two modes of o...

Page 943: ...ts 128 words 128 words Write to SD_DATA Write to card are two different transfers that occur at the same time and Write to the card SD_CMD DDIR 0 Interconnect bus Interconnect bus Card bus Card bus ME...

Page 944: ...re 9 12 Buffer Management for a Read 9 2 6 1 1 Memory Size Block Length and Buffer Management Relationship The maximum block length and buffer management that can be targeted by system depend on memor...

Page 945: ...ecification Part E1 or the SD Card Specification Part A2 SD Host Controller Standard Specification for more details Table 9 7 shows how the SD and SDIO responses are stored in the SD_RSPxx registers T...

Page 946: ...et upon DEB 21 DCRC 1 TC is set upon DCRC 20 DTO DTO and TC are mutually exclusive DCRC and DEB cannot occur with DTO 19 CIE 1 CC is set upon CIE 18 CEB 1 CC is set upon CEB 17 CCRC 1 CC can be set up...

Page 947: ...r R1b or R5b responses Figure 9 13 Busy Timeout for R1b R5b Responses t1 Data timeout counter is loaded and starts after R1b R5b response type t2 Data timeout counter stops and if it is 0 SD_STAT 21 D...

Page 948: ...1 Data timeout counter is loaded and starts after Data block CRC t2 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated 9 2 8 4 Read Data Timeout Figure 9 16 shows DCRC event condit...

Page 949: ...a timeout counter is loaded and starts t4 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated t5 Data timeout counter is loaded and starts after Data CRC transmission t6 Data timeou...

Page 950: ...been defined for SDR50 and SDR104 card components for write data transfers as auto command 12 end bit shall arrive after the CRC status end bit Figure 9 19 shows auto CMD12 timings during write trans...

Page 951: ...val in order to receive the last complete and reliable block SD controller only follows the Left Border Case defined by SD UHS specification Figure 9 20 shows ACMD12 timings during read transfer Figur...

Page 952: ...by setting the SD_HCTL 16 SBGR bit to 1 When enabled this capability holds the transfer on until the end of a block boundary If a stop transmission is needed software can use this pause to send a CMD1...

Page 953: ...ings In this case SD_HCTL 2 HSPE bit is cleared to 0 Figure 9 21 shows the output signals of the module when generating from the falling edge of the clock Figure 9 21 Output Driven on Falling Edge 9 2...

Page 954: ...setting Power on boot defines a way for the boot code to be accessed by the SD SDIO host controller without an upper level software driver speeding the time it takes for a controller to access the boo...

Page 955: ...token sent by the card Three cases can be met CCS is receive just before CCSD is emitted An interrupt CIRQ is generated with CCS detection CCSD is transmitted to card then an interrupt CC is generated...

Page 956: ...enable Status 10 BWE Indicates whether there is enough space in the buffer to write BLEN bytes of data Read transfer active Status 9 RTA This status is used for detecting completion of a read transfer...

Page 957: ...om the SD module See Interrupt INTC Controller chapter optional sDMA or dDMA DMA configuration must be done to enable the module DMA channel requests See SDMA chapter optional Interconnect For more in...

Page 958: ..._CAPA 26 24 and SD_CUR_CAPA 23 0 registers before the SD SDIO host driver is started 9 3 2 4 Wake Up Configuration Table 9 12 details SD controller wake up configuration Table 9 12 SD SDIO Controller...

Page 959: ...nternal clock Configure the SD_SYSCTL 15 6 CLKD bit field Read the SD_SYSCTL 1 ICS bit ICS 0x1 YES Clock is stable Write the SD_SYSCONFIG CLOCKACTIVITY SIDLEMODE and AUTOIDLE fields to configure the b...

Page 960: ...Clear SD_STAT register write 0xFFFF FFFF Change clock frequency to fit protocol Send a CMD0 command Preliminary Low Level Programming Models www ti com 9 3 3 Operational Modes Configuration 9 3 3 1 B...

Page 961: ...get information on how to access the card content MMC cards YES and all cards are not identified NO or all cards are identified Is there more than one MMC connected to the same bus and are they all i...

Page 962: ...and transfer mode Section 9 4 13 210h SD_RSP10 Command Response 0 and 1 Section 9 4 14 214h SD_RSP32 Command Response 2 and 3 Section 9 4 15 218h SD_RSP54 Command Response 4 and 5 Section 9 4 16 21Ch...

Page 963: ...i e typically the module s HDL generics if any Figure 9 30 SD_HL_HWINFO Register 31 16 Reserved R 0 15 2 1 0 Reserved MEM_SIZE MADMA_EN R 0 R 0 R x LEGENDR W Read Write R Read only n value after rese...

Page 964: ...is only relevant if the appropriate IP module mwake up output is implemented Functional clock is maintained Interface clock may be switched off 11 10 Reserved 0 These bits are initialized to zero and...

Page 965: ...utomatically reset by the hardware During reset it always returns 0 Read 0 Normal mode Write 0 No effect Read 1 The module is reset Write 1 Trigger a module reset 0 AUTOIDLE Internal Clock gating stra...

Page 966: ...ster enables the host controller to detect card status errors of response type R1 R1b for all cards and of R5 R5b and R6 response for cards types SD or SDIO When a bit SD_CSRE i is set to 1 if the cor...

Page 967: ...17 System Test Register SD_SYSTEST Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved bit field Do not write any value Reads return 0 16 OBI Out of band interrupt OBI data value...

Page 968: ...ction the DAT5 line is driven high If SD_SYSTEST 3 DDIR bit 1 input mode direction no effect 8 D4D DAT4 input output signal data value Read 0 If SD_SYSTEST 3 DDIR bit 1 input mode direction returns th...

Page 969: ...If SD_SYSTEST 3 DDIR bit 0 output mode direction the DAT0 line is driven high If SD_SYSTEST 3 DDIR bit 1 input mode direction no effect 3 DDIR Control of the DAT 7 0 pins direction Read 0 No action R...

Page 970: ...can be configured either edge sensitive with early de assertion on first access to SD_DATA register or late de assertion request remains active until last allowed data written into SD_DATA 0 Slave DMA...

Page 971: ...on SD_DAT1 line and minimize the leakage current of the buffers 0 Disable all the input buffers outside of a transaction 1 Disable all the input buffers except the buffer of SD_DAT1 outside of a tran...

Page 972: ...is bit this bit makes it easier Clock divider SD_SYSCTL 15 6 CLKD bits should be set to ensure that 80 clock periods are greater than 1ms Notein this mode there is no command sent to the card and no r...

Page 973: ...Read Write R Read only n value after reset Table 9 20 Card Status Response Error SD_SDMASA Field Descriptions Bit Field Value Description 31 0 SDMA_SYSADDR This register contains the system memory ad...

Page 974: ...ions during transfers may return an invalid value and write operation will be ignored In suspend context the number of blocks yet to be transferred can be determined by reading this register When rest...

Page 975: ...SD_CMD 31 16 the command register SD_CMD 15 0 the transfer mode This register configures the data and command transfers A write into the most significant byte send the command A write into SD_CMD 15...

Page 976: ...D15 or ACMD15 10h CMD16 or ACMD16 11h CMD17 or ACMD17 12h CMD18 or ACMD18 13h CMD19 or ACMD19 14h CMD20 or ACMD20 15h CMD21 or ACMD21 16h CMD22 or ACMD22 17h CMD23 or ACMD23 18h CMD24 or ACMD24 19h CM...

Page 977: ...sfer 20 CICE Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command If the index is...

Page 978: ...utomatically after the transfer completion of the last block The Host Driver shall not set this bit to issue commands that do not require CMD12 to stop data transfer In particular secure commands do n...

Page 979: ...mand Response 31 16 15 0 RSP0 Command Response 15 0 9 4 15 Command Response 63 32 Register SD_RSP32 This 32 bit register holds bits positions 63 32 of command response type R2 The command response 63...

Page 980: ...5 80 15 0 RSP4 Command Response 79 64 9 4 17 Command Response 127 96 Register SD_RSP76 This 32 bit register holds bits positions 127 96 of command response type R2 The command response 127 96 register...

Page 981: ...n 3 0 0010 1 byte Mbyteen 3 0 1100 2 bytes OK Mbyteen 3 0 0001 1 byte Mbyteen 3 0 0010 1 byte Mbyteen 3 0 0100 1 byte OK Mbyteen 3 0 0001 1 byte Mbyteen 3 0 0010 1 byte Mbyteen 3 0 1000 1 byte Bad The...

Page 982: ...these registers after reset depends on the SD_DAT lines level at that time 19 WP Write Protect SD SDIO1 only SDIO cards only This bit reflects the write protect input pin SDWP level The value of this...

Page 983: ...quest This bit is cleared to 0 when all data have been read by the local host after last block or after a stop at block gap request Read 0 No valid data on the SD_DAT lines Read 1 Read data transfer o...

Page 984: ...of the command response excepted if there is a command conflict error SD_STAT 17 CCRC bit or SD_STAT 18 CEB bit set to 1 or a Auto CMD12 is not executed SD_AC12 0 ACNE bit After the end bit of the co...

Page 985: ...0 Disable wake up on out of band Interrupt 1 Enable wake up on out of band Interrupt 26 REM Wake up event enable on SD card removal This bit enables wake up events for card removal assertion Wake up i...

Page 986: ...age level for the card according to the voltage supported by the system SD_CAPA 26 VS18 bit SD_CAPA 25 VS30 bit SD_CAPA 24 VS33 bit before starting a transfer 5h 1 8 V Typical 6h 3 0 V Typical 7h 3 3...

Page 987: ...dge of the SD Clock This bit shall not be set when dual data rate mode is activated in SD_CON DDR 0 Normal speed mode 1 High speed mode 1 DTW Data transfer width This bit must be set following a valid...

Page 988: ...ters are cleared by the SD_SYSCTL 26 SRD bit SD_DATA SD_PSTATEBRE BWE RTA WTA DLA and DATI SD_HCTLSBGR and CR SD_STATBRR BWR BGE and TC Interconnect is reinitialized NoteIf a soft reset is issued when...

Page 989: ...Clock Ref bypass 2h Clock Ref 2 3h Clock Ref 3 3FFh Clock Ref 1023 5 3 Reserved 0 Reserved bit field Do not write any value 2 CEN Clock enable This bit controls if the clock is provided to the card o...

Page 990: ...W 0 R W 0 LEGENDR W Read Write R Read only n value after reset Table 9 32 Interrupt Status Register SD_STAT Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved bit field Do not w...

Page 991: ...ng a 0 at the end bit position of read data on SD_DAT line or at the end position of the CRC status in write mode Read 0 No error Write 0 Status bit unchanged Read 1 Data end bit error Write 1 Status...

Page 992: ...his bit is set to 1 Therefore the host driver can efficiently test for an error by checking this bit first Writes to this bit are ignored Read 0 No interrupt Read 1 Error interrupt event s occurred 14...

Page 993: ...ed Write 1 Status is cleared 5 BRR Buffer read ready This bit is set automatically during a read operation to the card see class 2 block oriented read commands when one block specified by the SD_BLK 1...

Page 994: ...tate if the command has a busy notification capability In Read modeThis bit is automatically set on completion of a read transfer SD_PSTATE 9 RTA bit In write modeThis bit is set automatically on comp...

Page 995: ..._ENABLE BGE_ENABLE TC_ENABLE CC_ENABLE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGENDR W Read Write R Read only n value after reset Table 9 33 Interrupt SD Enable Register SD_IE Field Descript...

Page 996: ...During 1 bit mode if the interrupt routine does not remove the source of a card interrupt in the SDIO card the status bit is reasserted when this bit is set to 1 This bit must be set to 1 when enterin...

Page 997: ...it Field Value Description 1 TC_ENABLE Transfer completed interrupt enable 0 Masked 1 Enabled 0 CC_ENABLE Command completed interrupt enable 0 Masked 1 Enabled 997 SPRUGX9 15 April 2011 Secure Digital...

Page 998: ...W 0 R W 0 R W 0 LEGENDR W Read Write R Read only n value after reset Table 9 34 Interrupt Signal Enable Register SD_ISE Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved bit fi...

Page 999: ...g status bit During 1 bit mode if the interrupt routine does not remove the source of a card interrupt in the SDIO card the status bit is reasserted when this bit is set to 1 This bit must be set to 1...

Page 1000: ...t Field Value Description 1 TC_SIGEN Transfer completed signal status enable 0 Masked 1 Enabled 0 CC_SIGEN Command completed signal status enable 0 Masked 1 Enabled 1000 Secure Digital SD Secure Digit...

Page 1001: ...d 1 Command not issued 6 5 Reserved 0 Reserved bit field Do not write any value 4 ACIE Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 i...

Page 1002: ...ET signal Read 0 1 8 V not supported Write 0 1 8 V not supported Read 1 1 8 V supported Write 1 1 8 V supported 25 VS30 Voltage support 3 0V Initialization of this register via a write access to this...

Page 1003: ...es 15 14 Reserved 0 Reserved bit field Do not write any value 13 8 BCF Base clock frequency for clock provided to the card Read 0 The value indicating the base maximum frequency for the output clock p...

Page 1004: ...3 16 15 8 7 0 Reserved CUR_1V8 CUR_3V0 CUR_3V3 R 0 R W 0 R W 0 R W 0 LEGENDR W Read Write R Read only n value after reset Table 9 37 Maximum Current Capabilities Register SD_CUR_CAPA Field Description...

Page 1005: ...r reset Table 9 38 Force Event Register SD_FE Field Descriptions Bits Field Value Description 31 30 Reserved 0 Reserved bit field Any writes to these bits result in 0 29 FE_BADA Force Event Bad access...

Page 1006: ...mmand not issue by Auto CMD12 error Write 0 No effect no interrupt Write 1 Interrupt forced 6 5 Reserved 0 Reserved bit field Any writes to these bits result in 0 4 FE_ACIE Force Event Auto CMD12 inde...

Page 1007: ...r occurs at ST_FDS state The Host Driver may find that the Valid bit is not set in the error descriptor The ADMA error status register SD_BLK is shown in Figure 9 57 and described in Table 9 39 Figure...

Page 1008: ...e next line whenever fetching a Descriptor line When the ADMA Error Interrupt is generated this register holds the valid Descriptor address depending on the ADMA state The Host Driver shall program th...

Page 1009: ...VREV 0 Vendor Version Number Bits 7 4 is the major revision bits 3 0 is the minor revision Examples 10h for 1 0 21h for 2 1 23 16 SREV Specification Version Number This status indicates the Standard S...

Page 1010: ...1010 Secure Digital SD Secure Digital I O SDIO Card Interface SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1011: ...McASP This chapter describes the multichannel audio serial port McASP Topic Page 10 1 Introduction 1012 10 2 Architecture 1024 10 3 Registers 1067 1011 SPRUGX9 15 April 2011 Multichannel Audio Serial...

Page 1012: ...al converters ADC digital to analog converters DAC codec digital audio interface receiver DIR and S PDIF transmit physical layer components Wide variety of I2S and similar bit stream format Integrated...

Page 1013: ...its sets to 0 1 or extends value of another bit In DIT mode for McASP additional features of the transmitter are Transmit only mode 384 time slots subframe per frame Bi phase encoded 3 3 V output Supp...

Page 1014: ...el Pin function control Clock check circuit format unit Data port DAT Configuration bus CFG L3 Slow Interconnect L4 Slow Interconnect AXR5 Serializer 5 Preliminary Introduction www ti com 10 1 4 Funct...

Page 1015: ...Stereo I2S Preliminary www ti com Introduction 10 1 4 1 System Level Connections Figure 10 2 through Figure 10 6 show examples of McASP usage in digital audio encoder decoder systems Figure 10 2 McAS...

Page 1016: ...RF C LFE LS RS Stereo I2S 2 ch ADC 2 ch ADC 2 ch ADC 2 ch ADC 2 ch ADC 2 ch ADC 2 ch ADC 2 ch ADC RX DIT TX McASP 8 S PDIF encoded outputs Preliminary Introduction www ti com Figure 10 4 McASP to Dig...

Page 1017: ...the serial clock ACLKX or ACLKR The data bits are grouped into words and slots as defined in Section 10 1 7 The slots are also commonly referred to as time slots or channels in TDM terminology A fram...

Page 1018: ...ugh to transfer a total of 6 channels within each frame period Alternatively a similar six channel DAC may be designed to use three serial data pins AXR 0 1 2 transferring two channels of data on each...

Page 1019: ...1 is represented by two transitions of the signal within a time interval which corresponds to a cell with logical states 01 or 10 A logical 0 is represented by one transition within a time interval wh...

Page 1020: ...terval 29 carries the user data channel U associated with the main data field in the subframe Time interval 30 carries the channel status information C associated with the main data field in the subfr...

Page 1021: ...ic synchronous serial interface consists of three important components clock frame sync and data Figure 10 13 shows two of the three basic components the clock ACLK and the data AXRn Figure 10 13 does...

Page 1022: ...gn LSB first pad zeros 87h as 8 bit word 12 bit slot c right align LSB first pad zeros 87h as 8 bit word 12 bit slot d 87h as 8 bit word 12 bit slot left align MSB first pad with bit 7 e 87h as 8 bit...

Page 1023: ...nt transfer modes and protocols burst mode TDM mode and I2S format DIT mode and S PDIF format Figure 10 15 Definition of Frame and Frame Sync Width 1 In this example there are two slots in a frame and...

Page 1024: ...two independent clock zones transmit and receive clock zones The serial clock generators may be programmed independently for the transmit section and the receive section and may be completely asynchr...

Page 1025: ...CLKXP 0 the CLKXP mux directly passes ACLKX to XCLK As a result the McASP shifts transmit data at the rising edge of ACLKX If CLKXP 1 the CLKX mux passes the inverted version of ACLKX to XCLK As a re...

Page 1026: ...n to operate synchronously from the ACLKX and AFSX signals This is achieved when the ASYNC bit in the transmit clock control register ACLKXCTL is cleared to 0 see Figure 10 17 The receiver may be conf...

Page 1027: ...SXCTL The options are Internally generated or externally generated Frame sync polarity rising edge or falling edge Frame sync width single bit or single word Bit delay 0 1 or 2 cycles before the first...

Page 1028: ...ns The signals used on the McASP audio interface are listed in Table 10 3 Table 10 3 McASP Interface Signals Device Reset Pin I O Z RESET 0 Description Transmitter Control AHCLKX I O Z Input Transmit...

Page 1029: ...the receive frame sync internally frame sync begins when the previous transmission has completed and when all the RBUF n for every serializer set to operate as a receiver has been read Figure 10 19 Bu...

Page 1030: ...receive AHCLKR as an input See Section 10 2 2 2 and Section 10 2 2 3 The control registers must be configured as follows for the TDM mode The TDM mode specific bit fields are in bold face PFUNC The c...

Page 1031: ...t is generated Transmit pins are automatically set to a high impedance state 0 or 1 during that slot as determined by bit DISMOD in SRCTL n Figure 10 20 shows when the transmit DMA event AXEVT is gene...

Page 1032: ...n different systems through an optical or coaxial cable The DIT mode only applies to serializers configured as transmitters not receivers Refer to Section 10 1 6 2 for a description of the S PDIF form...

Page 1033: ...face PFUNC The data pins must be configured for McASP function If AHCLKX is used it must also be configured for McASP function PDIR The data pins must be configured as outputs If AHCLKX is used as an...

Page 1034: ...is being used It is a requirement that the software avoid writing to the word of user data and channel status that are being used to encode the current time slot otherwise it will be indeterminate whe...

Page 1035: ...ined by DITCSRA2 DITCSRB2 DITUDRA2 DITUDRB2 64 1 L M DITCSRA2 0 DITUDRA2 0 64 2 R W DITCSRB2 0 DITUDRB2 0 95 1 L M DITCSRA2 31 DITUDRA2 31 95 2 R W DITCSRB2 31 DITUDRB2 31 Defined by DITCSRA3 DITCSRB3...

Page 1036: ...RBUF register which is an alias of the XRBUF for receive When the processor reads from the RBUF the McASP passes the data from RBUF through the receive format unit and returns the formatted data to th...

Page 1037: ...of three stages Bit mask and pad masks off bits performs sign extension Rotate right aligns data within word Bit reversal selects between MSB first or LSB first Figure 10 22 shows a block diagram of...

Page 1038: ...serial transfers can occur until the respective state machine is released from reset See initialization sequence for details Section 10 2 10 The receive state machine is controlled by the RFMT registe...

Page 1039: ...respective PDOUT n to 0 Writing a 0 has no effect Applicable only when the pin is configured as GPIO output PFUNC n 1 and PDIR n 1 See the register descriptions in Section 10 3 for details on the mapp...

Page 1040: ...discussed in Section 10 2 8 1 4 and Section 10 2 12 2 10 2 8 1 1 Data Ready Status and Event Interrupt Generation 10 2 8 1 1 1 Transmit Data Ready The transmit data ready flag XDATA bit in the XSTAT r...

Page 1041: ...is 32 bit With the above setup we obtain the following parameters corresponding to Figure 10 25 Calculation of McASP system clock cycle C64x DSP uses SYSCLK2 as the McASP system clock It runs at 150 M...

Page 1042: ...s that even if RSTAT already has the RDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep only one DMA event is generated to...

Page 1043: ...s active and transmit within each time slot Failure to do so results in a buffer underrun condition Section 10 2 8 4 2 Similarly when receiving data must be read from each serializer configured as act...

Page 1044: ...block diagram of the AFIFO The AFIFO may be enabled disabled and configured via the WFIFOCTL and RFIFOCTL registers Note that if the Read or Write FIFO is to be enabled it must be enabled prior to ini...

Page 1045: ...DMA request the RFIFO reads RNUMDMA 32 bit words from the McASP if and when the RFIFO has space for RNUMDMA words If it does not the RFIFO waits until this condition has been satisfied at that point i...

Page 1046: ...request and receive DMA request occur simultaneously priority is given to the receive DMA request Once a transfer is in progress it is allowed to complete 1046 Multichannel Audio Serial Port McASP SPR...

Page 1047: ...the bit mask pad unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a wor...

Page 1048: ...P P XROT WORD e Out MSB first LEFT aligned M M 1 L P P XRVRS 1 reverse P P L M 1 M REP Integer P L M P M 1 Data flow P P P P M M 1 L XROT SLOT P P f Out MSB first RIGHT aligned XRVRS 1 reverse P P M M...

Page 1049: ...w for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot siz...

Page 1050: ...D 32 REP Q31 M L M 1 P P RROT 0 M M 1 L P P M M 1 L P P RRVRS 0 no reverse RROT 0 M 1 P P M L RRVRS 1 reverse f In MSB first RIGHT aligned P P M M 1 L L M 1 M P P Data flow Data flow Data flow Data fl...

Page 1051: ...pected receive frame sync occurs Current frame is not resynchronized The number of bits in the current frame is completed The next frame sync which occurs after the current frame is completed will be...

Page 1052: ...DMA should write exactly as many words as there are serializers enabled as transmitters XDMAERR indicates that the DMA or CPU wrote too many words to the McASP for a given transmit DMA event Writing...

Page 1053: ...following may be enabled i transmit clock failure interrupt enable bit XCKFAIL in the transmitter interrupt control register XINTCTL ii transmit clock failure detect autoswitch enable bit XCKFAILSW i...

Page 1054: ...t XCKFAIL in XSTST when an out of range condition occurs An out of range minimum condition occurs when the count is smaller than XMIN The logic continually compares the current count from the running...

Page 1055: ...ock it produces is a full period However the transmit clock divide ratio bits HCLKXDIV in AHCLKXCTL are not affected so the internal clock divider generates clocks at the rate configured 3 The transmi...

Page 1056: ...minimum condition occurs when the count is smaller than RMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary RMAX This is...

Page 1057: ...shows the basic logical connection of the serializers in loopback mode Two types of loopback connections are possible selected by the ORD bit in the digital loopback control register DLBCTL as follow...

Page 1058: ...and or receive in order to assert the software reset bits in GBLCTL see Section 10 2 10 2for details on how to ensure reset has occurred The entire McASP module may also be reset through the Power and...

Page 1059: ...Global registers Registers PFUNC PDIR DITCTL DLBCTL AMUTE Note that PDIR should only be programmed after the clocks and frames are set up in the steps above This is because the moment a clock pin is...

Page 1060: ...ore proceeding in this step you should verify that the XDATA bit in the XSTAT is cleared to 0 indicating that all transmit buffers are already serviced by the DMA b If CPU interrupt is used to service...

Page 1061: ...oes not have a time out and the bit clock stops the changes written to GBLCTL will not be reflected until the bit clock restarts Finally please note that while RGBLCTL and XGBLCTL allow separate chang...

Page 1062: ...transmit frame sync A transmit last slot interrupt XLAST is a qualified version of the data ready interrupt XDATA It has the same behavior as the data ready interrupt but is further qualified by havi...

Page 1063: ...dware the AMUTE pin to a preprogrammed output state as selected by the MUTEN bit in the audio mute control register AMUTE The AMUTE pin is asserted when one of the interrupt flags is set or an externa...

Page 1064: ...nding interrupt request is allowed on each port so a transmit and a receive interrupt request may both be outstanding at the same time 10 2 12 EDMA Event Support 10 2 12 1 EDMA Events There are 6 EDMA...

Page 1065: ...C and time slot for channels RF RS LFE Similarly AREVT is triggered for each of the receive audio channel time slot Scenario 1 allows for the use of a single DMA to transmit all audio channels and a s...

Page 1066: ...time slot while each receive DMA request is for data in the previous time slot For example Figure 10 37 shows a circled AXEVTE event for an even time slot transmit DMA request The transmitter always r...

Page 1067: ...GBLCTL Global control register Section 10 3 8 48h AMUTE Audio mute control register Section 10 3 9 4Ch DLBCTL Digital loopback control register Section 10 3 10 50h DITCTL DIT mode control register Sec...

Page 1068: ...CSRA5 Left even TDM time slot channel status register DIT mode 5 Section 10 3 37 118h DITCSRB0 Right odd TDM time slot channel status register DIT mode 0 Section 10 3 38 11Ch DITCSRB1 Right odd TDM ti...

Page 1069: ...1 204h XBUF1 Transmit buffer register for serializer 1 Section 10 3 41 208h XBUF2 Transmit buffer register for serializer 2 Section 10 3 41 20Ch XBUF3 Transmit buffer register for serializer 3 Section...

Page 1070: ...004h WFIFOSTS Write FIFO status register Section 10 3 44 1008h RFIFOCTL Read FIFO control register Section 10 3 45 100Ch RFIFOSTS Read FIFO status register Section 10 3 46 10 3 1 Revision Identificati...

Page 1071: ...value other than 0 to reserved bits in this register may cause improper device operation Figure 10 39 Pin Function Register PFUNC 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Rese...

Page 1072: ...ines if AHCLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 26 ACLKX Determines if ACLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin fu...

Page 1073: ...be set to 1 an output When AXRn is configured to transmit the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be set to 1 an output Similarly when AXRn is configured to receive th...

Page 1074: ...ines if AHCLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 26 ACLKX Determines if ACLKX pin functions as an input or output 0 Pin functions as input 1 Pin fu...

Page 1075: ...riting a 0 has no effect and keeps the bits in PDOUT unchanged PDCLR when written to at this address writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0 writing a 0 has no effect...

Page 1076: ...rmines drive on AHCLKX output pin when the corresponding PFUNC 27 and PDIR 27 bits are set to 1 0 Pin drives low 1 Pin drives high 26 ACLKX Determines drive on ACLKX output pin when the corresponding...

Page 1077: ...Table 10 14 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 10 42 Pin Data Input Register PDIN 31 30 29 28 27...

Page 1078: ...level on AHCLKX pin 0 Pin is logic low 1 Pin is logic high 26 ACLKX Logic level on ACLKX pin 0 Pin is logic low 1 Pin is logic high 25 AMUTE Logic level on AMUTE pin 0 Pin is logic low 1 Pin is logic...

Page 1079: ...ed by the same McASP The PDSET is shown in Figure 10 43 and described in Table 10 15 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper...

Page 1080: ...the corresponding AHCLKX bit in PDOUT to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is set to 1 26 ACLKX Allows the corresponding A...

Page 1081: ...lled by the same McASP The PDCLR is shown in Figure 10 44 and described in Table 10 16 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause imprope...

Page 1082: ...s the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is cleared to 0 26 ACLKX Allows the corresp...

Page 1083: ...clocks and generating frame sync as programmed 11 XSMRST Transmit state machine reset enable bit 0 Transmit state machine is held in reset AXRn pin state If PFUNC n 0 and PDIR n 1 then the serializer...

Page 1084: ...ed from reset When released from reset the receive state machine immediately begins detecting frame sync and is ready to receive Receive TDM time slot begins at slot 0 after reset is released 2 RSRCLR...

Page 1085: ...active and is driven according to MUTEN bit 10 XCKFAIL If transmit clock failure XCKFAIL drive AMUTE active enable bit 0 Drive is disabled Detection of transmit clock failure is ignored by AMUTE 1 Dri...

Page 1086: ...dio mute in error is detected 3 INEN Drive AMUTE active when AMUTEIN error is active INSTAT 1 0 Drive is disabled AMUTEIN is ignored by AMUTE 1 Drive is enabled active INSTAT 1 drives AMUTE active 2 I...

Page 1087: ...3 2 MODE 0 3h Loopback generator mode bits Applies only when loopback mode is enabled DLBEN 1 0 Default and reserved on loopback mode DLBEN 1 When in non loopback mode DLBEN 0 MODE should be left at d...

Page 1088: ...d time slots DIT right subframe 0 V bit is 0 during odd DIT subframes 1 V bit is 1 during odd DIT subframes 2 VA Valid bit for even time slots DIT left subframe 0 V bit is 0 during even DIT subframes...

Page 1089: ...it value of GBLCTL Writes have no effect 9 XHCLKRST x Transmit high frequency clock divider reset enable bit A read of this bit returns the XHCLKRST bit value of GBLCTL Writes have no effect 8 XCLKRST...

Page 1090: ...END R W Read Write n value after reset Table 10 22 Receive Format Unit Bit Mask Register RMASK Field Descriptions Bit Field Value Description 31 0 RMASK 31 0 Receive data mask n enable bit 0 Correspon...

Page 1091: ...cycle as the receive frame sync AFSR 1h 1 bit delay The first receive data bit AXRn occurs one ACLKR cycle after the receive frame sync AFSR 2h 2 bit delay The first receive data bit AXRn occurs two...

Page 1092: ...guration bus CFG or the data DAT port 0 Reads from XRBUF n originate on data port Reads from XRBUF n on configuration bus are ignored 1 Reads from XRBUF n originate on configuration bus Reads from XRB...

Page 1093: ...external DIR IC inputting 384 slot DIR frames to McASP over I2S interface 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this...

Page 1094: ...lock so the external transmitter driving this receiver must shift data out on the rising edge of the serial clock 1 Rising edge Receiver samples data on the rising edge of the serial clock so the exte...

Page 1095: ...lock source from output of programmable high clock divider 14 HCLKRP Receive bitstream high frequency clock polarity select bit 0 AHCLKR is not inverted before programmable bit clock divider In the sp...

Page 1096: ...D R W Read Write n value after reset Table 10 27 Receive TDM Time Slot Register RTDM Field Descriptions Bit Field Value Description 31 0 RTDMS 31 0 Receiver mode during TDM time slot n 0 Receive TDM t...

Page 1097: ...bility 5 RDATA Receive data ready interrupt enable bit 0 Interrupt is disabled A receive data ready interrupt does not generate a McASP receive interrupt RINT 1 Interrupt is enabled A receive data rea...

Page 1098: ...this bit has no effect 0 Receive DMA error did not occur 1 Receive DMA error did occur 6 RSTAFRM Receive start of frame flag Causes a receive interrupt RINT if this bit is set and RSTAFRM in RINTCTL i...

Page 1099: ...ur 1 Receiver overrun did occur 10 3 21 Current Receive TDM Time Slot Registers RSLOT The current receive TDM time slot register RSLOT indicates the current time slot for the receive data frame The RS...

Page 1100: ...current counter value is greater than RMAX after counting 32 AHCLKR signals RCKFAIL in RSTAT is set The comparison is performed using unsigned arithmetic 15 8 RMIN 0 FFh Receive clock minimum boundar...

Page 1101: ...A R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 32 Receiver DMA Event Control Register REVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The re...

Page 1102: ...set 1 Transmit state machine is released from reset 10 XSRCLR Transmit serializer clear enable bit A write to this bit affects the XSRCLR bit of GBLCTL 0 Transmit serializers are cleared 1 Transmit se...

Page 1103: ...eset Table 10 34 Transmit Format Unit Bit Mask Register XMASK Field Descriptions Bit Field Value Description 31 0 XMASK 31 0 Transmit data mask n enable bit 0 Corresponding bit of transmit data before...

Page 1104: ...transmit frame sync AFSX 1h 1 bit delay The first transmit data bit AXRn occurs one ACLKX cycle after the transmit frame sync AFSX 2h 2 bit delay The first transmit data bit AXRn occurs two ACLKX cyc...

Page 1105: ...0 Writes to XRBUF n originate from the data port Writes to XRBUF n from the configuration bus are ignored with no effect to the McASP 1 Writes to XRBUF n originate from the configuration bus Writes to...

Page 1106: ...17Fh Reserved 180h 384 slot DIT mode 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to th...

Page 1107: ...Rising edge External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock 1 Falling edge External receiver sampl...

Page 1108: ...y clock source from output of programmable high clock divider 14 HCLKXP Transmit bitstream high frequency clock polarity select bit 0 AHCLKX is not inverted before programmable bit clock divider In th...

Page 1109: ...re 10 67 Transmit TDM Time Slot Register XTDM 31 0 XTDMS n R W 0 LEGEND R W Read Write n value after reset Table 10 39 Transmit TDM Time Slot Register XTDM Field Descriptions Bit Field Value Descripti...

Page 1110: ...ATA Transmit data ready interrupt enable bit 0 Interrupt is disabled A transmit data ready interrupt does not generate a McASP transmit interrupt XINT 1 Interrupt is enabled A transmit data ready inte...

Page 1111: ...as no effect 0 Transmit DMA error did not occur 1 Transmit DMA error did occur 6 XSTAFRM Transmit start of frame flag Causes a transmit interrupt XINT if this bit is set and XSTAFRM in XINTCTL is set...

Page 1112: ...itions 10 3 33 Current Transmit TDM Time Slot Register XSLOT The current transmit TDM time slot register XSLOT indicates the current time slot for the transmit data frame The XSLOT is shown in Figure...

Page 1113: ...e current counter value is greater than XMAX after counting 32 AHCLKX signals XCKFAIL in XSTAT is set The comparison is performed using unsigned arithmetic 15 8 XMIN 0 FFh Transmit clock minimum bound...

Page 1114: ...DMA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 44 Transmitter DMA Event Control Register XEVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved T...

Page 1115: ...to RBUF 0 Receive buffer RBUF is empty 1 Receive buffer RBUF contains data and needs to be read before the start of the next time slot or a receiver overrun occurs 4 XRDY Transmit buffer ready bit XR...

Page 1116: ...SRB n R W 0 LEGEND R W Read Write n value after reset 10 3 39 DIT Left Channel User Data Registers DITUDRA0 DITUDRA5 The DIT left channel user data registers DITUDRA provides the user data of each lef...

Page 1117: ...R W Read Write n value after reset 10 3 42 Receive Buffer Registers RBUFn The receive buffers for the serializers RBUF hold data from the serializer before the data goes to the receive format unit For...

Page 1118: ...d 1 Write FIFO is enabled If Write FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 WNUMEVT 0 FFh Write word count per DMA event 32 bit When the Write FIFO has space fo...

Page 1119: ...et Table 10 47 Write FIFO Status Register WFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 WLVL 0 FFh Write level read only Number of 32 bit words currently in the...

Page 1120: ...IFO is flushed 1 Read FIFO is enabled If Read FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 RNUMEVT 0 FFh Read word count per DMA event 32 bit When the Read FIFO con...

Page 1121: ...eset Table 10 49 Read FIFO Status Register RFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RLVL 0 FFh Read level read only Number of 32 bit words currently in the...

Page 1122: ...1122 Multichannel Audio Serial Port McASP SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1123: ...BSP This chapter introduces the multichannel buffered serial port McBSP Topic Page 11 1 Introduction 1124 11 2 Architecture 1126 11 3 Registers 1176 1123 SPRUGX9 15 April 2011 Multichannel Buffered Se...

Page 1124: ...election of data sizes 8 12 16 20 24 and 32 bits Bit reordering send receive LSB Status bits for flagging exception error conditions Full Half cycle mode on both transmit and receive side Note SC_McBS...

Page 1125: ...www ti com Introduction 11 1 3 Block Diagram Figure 11 1 McBSP Block Diagram 1125 SPRUGX9 15 April 2011 Multichannel Buffered Serial Port McBSP Submit Documentation Feedback 2011 Texas Instruments In...

Page 1126: ...value If there is no previous data in transmit shift register the value from the transmit buffer is copied to transmit shift register otherwise the content is copied to transmit shift register when t...

Page 1127: ...l serial word Only then is the word passed to the receive buffer RB and ultimately to the DRR_REG register During transmission XSR accept new data from transmit buffer XB after a full serial word has...

Page 1128: ...d frame length or number of words is reached For more details on unexpected frame synchronization pulses see Section 11 2 3 2 and Section 11 2 3 5 11 2 1 3 6 Frame Frequency The frame frequency is det...

Page 1129: ...R1_REG and RCR2_REG and in the transmit control registers XCR1_REG and XCR2_REG determine the number of phases per frame the number of words per frame and the number of bits per word for each phase fo...

Page 1130: ...RCR2_REG 14 8 and XWDLEN2 XCR2_REG 14 8 are ignored CLKRP PCR_REG 0 and CLKXP PCR_REG 1 0 Receive data clocked on falling edge transmit data clocked on rising edge FSRP PCR_REG 2 and FSXP PCR_REG 3 0...

Page 1131: ...ropriate data delay that is selected with the RDATDLY bits of RCR2_REG 1 0 register In the preceding timing diagram a 1 bit data delay is selected 3 The McBSP accepts data bits on the McBSP DR pin and...

Page 1132: ...1 register to indicate that the transmitter is not ready for new data 2 When new data arrives in DXR_REG register the McBSP copies the content of the data transmit register to the transmit buffer In...

Page 1133: ...ata clock CLKG and an internal frame synchronization signal FSG CLKG can be used for bit shifting on the data receive McBSP DR pin and or the data transmit McBSP DX pin FSG can be used to initiate fra...

Page 1134: ...f CLKRM 1 and CLKXM 1 on the McBSP are partially affected by the use of the digital loop back mode the analog loop back mode and by the synchronous receive transmit setting respectively as described i...

Page 1135: ...hat transmit frame synchronization is supplied by the McBSP itself rather than from the McBSP FSX pin FSGM 1 in SRGR2_REG 12 register This indicates that when FSXM 1 transmit frame synchronization is...

Page 1136: ...d on FSG is determined by the arrival of the next frame synchronization pulse on the McBSP FSR pin If GSYNC 0 CLKG runs freely and is not resynchronized and the frame synchronization period on FSG is...

Page 1137: ...esync FSR external FSRP 0 CLKS CLKSP 0 CLKS CLKSP 1 Preliminary www ti com Architecture Figure 11 12 CLKG Synchronization and FSG Generation GSYNC 1 and CLKGDV 1 Figure 11 13 CLKG Synchronization and...

Page 1138: ...ets the RSYNCERR bit in SPCR1_REG Receiver Underflow RUNDFLSTAT bit is set to 1 in IRQSTATUS register This occurs when DMA controller or CPU reads data from an empty receive buffer Transmitter Underfl...

Page 1139: ...ed data arriving on McBSP DR is continuously shifted into Once a complete word is shifted into the RSR an RSR to RB copy can occur only if the RB is not full Either of the following events clears the...

Page 1140: ...the interrupt Using the legacy mode RSYNCERR bit in SPCR1_REG can be cleared only by a receiver reset or by a write of 0 to this bit If you want the McBSP to notify the CPU of receive frame synchroni...

Page 1141: ...by setting the XUNDFLSTAT bit in IRQSTATUS register Also the legacy mode XEMPTY bit in SPCR2_REG 2 register is cleared Either of the following events activates XEMPTY XEMPTY 0 DXR_REG has not been lo...

Page 1142: ...ster will clear the interrupt Using the legacy mode XSYNCERR bit in SPCR2_REG can be cleared only by a transmitter reset or by a write of 0 to this bit If you want the McBSP to notify the CPU of frame...

Page 1143: ...of the transfer is the same as the threshold value plus one As long as the RB occupied locations level is above or equal to the THRSH1_REG value plus one the DMA request will be asserted After transfe...

Page 1144: ...ppropriate multichannel selection mode is on each bit in the register controls whether data flow is allowed or prevented in one of the channels that is assigned to that partition The McBSP has one rec...

Page 1145: ...s 80 through 95 RCERF_REG G Block 6 channels 96 through 111 RCERG_REG H Block 7 channels 112 through 127 RCERH_REG Table 11 5 Eight Partitions Transmit Channel Assignment and Control Register Used for...

Page 1146: ...ssion McBSP channels are activated using an alternating scheme In response to a frame synchronization pulse the receiver or transmitter begins with the channels in partition A and then alternates betw...

Page 1147: ...in channel 15 Places the McBSP DX pin in the high impedance state in channels 16 38 Shifts data to the McBSP DX pin in channel 39 Table 11 6 Selecting a Transmit Multichannel Selection Mode with the...

Page 1148: ...ms where symmetric transmit and receive provide software benefits this feature allows transmit channels to be disabled on a shared serial bus A similar feature is not needed for reception because mult...

Page 1149: ...d reception are symmetric which means the corresponding bits for the receiver RPHASE RFRLEN1 RWDLEN1 and RMCME must have the same values as XPHASE XFRLEN1 and XWDLEN1 respectively In Figure 11 21 the...

Page 1150: ...XPABLK 00b XCERA 1010b All channels enabled only 1 and 3 unmasked Words W0 W1 W2 W3 are written to the transmit buffer but only W1 and W3 from the transmit buffer are transferred by McBSP DX d XMCM 1...

Page 1151: ...nsmit Full Cycle Mode Data driven on positive CLKX edge FSX sampled on positive CLKX edge 11 2 6 2 Transmit Half Cycle Mode When configured in half cycle mode XCCR 11 register XFULL_CYCLE bit field th...

Page 1152: ...ve CLKR edge FSR sampled on negative CLKR edge 11 2 6 4 Receive Half Cycle Mode When configured in half cycle mode RCCR 11 register RFULL_CYCLE bit field the FSR is sampled on the opposite configured...

Page 1153: ...when exit from idle mode RSYNCERREN The McBSP asserts the McBSP WAKEUP request when an unexpected receive frame sync pulse is detected If the corresponding bit is set in IRQENABLE register McBSP send...

Page 1154: ...old synchronization only when wake up event is set on transmit receive threshold reached When CLKR is used as source functional clock is provided from outside then the module will acknowledge the Smar...

Page 1155: ...e implementing such a feature to use this type of error in order to trigger a wake up This mode requires functional clock to be active When McBSP FSR McBSP FSX is configured as an output the McBSP FSR...

Page 1156: ...PCR1_REG 0 and reset the transmitter SPCR2_REG 0 register XRST bit 0 2 Program the registers that affect the sample rate generator Program the sample rate generator registers SPCR1_REG and SPCR2_REG a...

Page 1157: ...transmit interrupt request line The legacy interrupt compliant scheme using 3 interrupt lines one for receive one for transmit and the receive overflow interrupt line The OCP compliant interrupt line...

Page 1158: ...extension and justification mode 7 Set the receive interrupt mode Frame synchronization behavior 1 Set the receive frame synchronization mode 2 Set the receive frame synchronization polarity 3 Set th...

Page 1159: ...ed to the CLKX output pin CLKXO This mode allows testing of serial port the McBSP receives the data it transmits This loop back mode is not done through pads all output signals being disabled CLKREN C...

Page 1160: ...transfer option is chosen for McBSP reception 11 2 8 5 12 Set the Receive Data Delay The RDATDLY bit field RCR2_REG 1 0 determines the length of the data delay for the receive frame The start of a fra...

Page 1161: ...igure 11 27 2 Bit Data Delay Used to Skip a Framing Bit 11 2 8 5 13 Set the Receive Sign Extension and Justification Mode The RJUST bit field SPCR1_REG 14 13 determines whether data received by the Mc...

Page 1162: ...INTM 10 and RSYNCERREN is equivalent with RINTM 11 setting This interrupt line has its own status register 11 2 8 5 15 Set the Receive Frame Sync Mode FSRM bit PCR_REG 10 GSYNC bit SRGR2_REG 15 ALB bi...

Page 1163: ...als are inverted before being sent to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization FSR FSX are output pins and GSYNC 0 is selected the internal active h...

Page 1164: ...LKG periods FPER 15 or 0000 1111b and a frame synchronization pulse with an active width of 2 CLKG periods FWID 1 When the sample rate generator comes out of reset FSG is in its inactive state Then wh...

Page 1165: ...to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization FSR FSX are output pins and GSYNC 0 is selected the internal active high frame synchronization signals...

Page 1166: ...signal CLKG and a frame synchronization signal FSG for use by the receiver the transmitter or both To produce CLKG and FSG the sample rate generator must be driven by an input clock signal derived fro...

Page 1167: ...serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the SPCR1_REG register The sample rate generator can be reset directly using the GRST bit in SPCR2_REG regist...

Page 1168: ...ow up to 128 words per phase See Table 11 15 for a summary of how to calculate the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronizati...

Page 1169: ...1 and thus on McBSP DX The transmitter then asynchronously detects the frame synchronization signal FSX going active high and immediately starts driving the first bit to be transmitted on the McBSP DX...

Page 1170: ...t SRGR2_REG 12 are used to set the transmit frame sync mode Table 11 16 shows how FSXM and FSGM select the source of transmit frame synchronization pulses The three choices are 1 External frame synchr...

Page 1171: ...the rising edge of internal CLKX If CLKXP 1 and external clocking is selected CLKXM 0 and CLKX is an input the external falling edge triggered input clock on CLKX is inverted to a rising edge triggere...

Page 1172: ...riods and Active Width of 2 CLKG Periods 11 2 8 6 16 Set the Transmit Clock Mode CLKXM bit PCR_REG 9 is used to set the transmit clock mode Table 11 17 shows how the CLKXM bit selects the transmit clo...

Page 1173: ...sent to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization FSR FSX are output pins and GSYNC 0 is selected the internal active high frame synchronization sign...

Page 1174: ...bit SRGR2_REG 13 are used to set the SRG clock mode The sample rate generator can produce a clock signal CLKG for use by the receiver the transmitter or both but CLKG is derived from an input clock 1...

Page 1175: ...reset XRST 0 in SPCR2_REG 0 2 General purpose I O is enabled for the serial port transmitter XIOEN 1 in PCR_REG 12 The McBSP CLKX and McBSP FSX pins can be individually configured as input or output...

Page 1176: ...E Section 11 3 22 60h RCERF_REG McBSP receive channel enable register partition F Section 11 3 23 64h XCERE_REG McBSP transmit channel enable register partition E Section 11 3 24 68h XCERF_REG McBSP t...

Page 1177: ...lue Description 31 0 DRR 0 Data receive register 11 3 2 McBSP Data Transmit Register DXR_REG The McBSP_DXR_REG register is shown in Figure 11 34 and described in Table 11 21 Figure 11 34 McBSP_DRR_REG...

Page 1178: ...t 0 Frame synchronization logic is reset Frame sync signal FSG is not generated by the sample rate generator 1 Frame sync signal FSG is generated after FPER 1 number of CLKG clocks i e all frame count...

Page 1179: ...cription 0 XRST Transmitter reset This resets and enables the transmitter 0 The serial port transmitter is disabled and in reset state 1 The serial port transmitter is enabled 1179 SPRUGX9 15 April 20...

Page 1180: ...abler is on 6 Reserved 0 Reserved 5 4 RINTM Receive Interrupt Mode legacy 0 Receive Interrupt driven by RRDY i e end of word and end of frame in A bis mode 1h Receive Interrupt generated by end of blo...

Page 1181: ...14 8 RFRLEN2 Receive Frame Length 2 Single phase frame selected RFRLEN2 don t care Dual phase frame selected RFRLEN2 000 0000 1 word per second phase other values are reserved 7 5 RWDLEN2 Receive Wor...

Page 1182: ...tion 31 15 Reserved 0 Reserved 14 8 RFRLEN1 Receive Frame Length 1 Single phase frame selected RFRLEN1 000 0000 1 word per frame RFRLEN1 000 0001 2 words per frame RFRLEN1 111 1111 128 words per frame...

Page 1183: ...14 8 XFRLEN2 Transmit Frame Length 2 Single phase frame selected XFRLEN2 don t care Dual phase frame selected XFRLEN2 000 0000 1 word per second phase Other values are reserved 7 5 XWDLEN2 Transmit Wo...

Page 1184: ...tion 31 15 Reserved 0 Reserved 14 8 XFRLEN1 Transmit Frame Length 1 Single phase frame selected XFRLEN1 000 0000 1 word per frame XFRLEN1 000 0001 2 words per frame XFRLEN1 111 1111 128 words per fram...

Page 1185: ...l frame sync pulse 14 CLKSP CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock CLKSM 0 0 Rising edge of CLKG and FSG 1 Falling edge of CLKG and FSG 13 CLKSM Mc...

Page 1186: ...McBSP_SRGR1_REG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8 FWID 0 Frame Width This value 1 determines the width of the frame sync pulse FSG during its active period...

Page 1187: ...n and reception assign 16 channels to receive partition A with the RPABLK bits Assign 16 channels to receive partition B with the RPBBLK bits You control the channels with the appropriate transmit cha...

Page 1188: ...R A B appropriately Also these selected channels are not masked and therefore DX is always driven 2h All channels enabled but masked Selected channels enabled via XP A B BLK and XCER A B are unmasked...

Page 1189: ...to partition B with the RPBBLK bits You can control the channels with the appropriate receive channel enable registers RCERA Channels in partition A RCERB Channels in partition B 1 8 partition mode Al...

Page 1190: ...nnel Enable RCERA n 0 Disables reception of n th channel in an even numbered block in partition A RCERA n 1 Enables reception of n th channel in an even numbered block in partition A 11 3 14 McBSP Rec...

Page 1191: ...channel in an event numbered block in partition A 11 3 16 McBSP Transmit Channel Enable Register Partition B XCERB_REG The McBSP_XCERB_REG register is shown in Figure 11 48 and described in Table 11...

Page 1192: ...eration 12 RIOEN Receive General Purpose I O Mode when RRST 0 in SPCR 1 2 legacy 0 DR FSR CLKR and CLKS are configured as serial port pins and do not function as general purpose I Os 1 DR and CLKS pin...

Page 1193: ...OCP clock 1 CLKSM 0 Signal on CLKR pin CLKSM 1 Signal on CLKX pin 6 CLKS_STAT CLKS pin status Reflects value on CLKS pin when selected as a general purpose input legacy 0 The signal on the CLKS pin is...

Page 1194: ...channel in an even numbered block in partition C 11 3 19 McBSP Receive Channel Enable Register Partition D RCERD_REG The McBSP_RCERD_REG register is shown in Figure 11 51 and described in Table 11 38...

Page 1195: ...channel in an event numbered block in partition C 11 3 21 McBSP Transmit Channel Enable Register Partition D XCERD_REG The McBSP_XCERD_REG register is shown in Figure 11 53 and described in Table 11...

Page 1196: ...channel in an even numbered block in partition E 11 3 23 McBSP Receive Channel Enable Register Partition F RCERF_REG The McBSP_RCERF_REG register is shown in Figure 11 55 and described in Table 11 42...

Page 1197: ...h channel in an event numbered block in partition E 11 3 25 McBSP Transmit Channel Enable Register Partition F XCERF_REG The McBSP_XCERF_REG register is shown in Figure 11 57 and described in Table 11...

Page 1198: ...channel in an even numbered block in partition G 11 3 27 McBSP Receive Channel Enable Register Partition H RCERH_REG The McBSP_RCERH_REG register is shown in Figure 11 59 and described in Table 11 46...

Page 1199: ...11 61 and described in Table 11 48 Figure 11 61 McBSP_XCERH_REG 31 16 15 0 Reserved XCERH R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 48 McBSP_XCERH_REG Field Descriptions...

Page 1200: ...ad Write n value after reset Table 11 51 McBSP_XINTCLR_REG Field Descriptions Bit Field Value Description 15 0 XINTCLR 0 Transmit Interrupt Clear legacy Read from this register will clear the IRQ gene...

Page 1201: ...witched off 1 OCP clock is maintained during wake up period Bit 9 Functional clock 0 Functional clock can be switched off 1 Functional clock is maintained during wake up period 7 5 Reserved 0 Reserved...

Page 1202: ...mit data DMA request if transmit DMA is enabled 11 3 36 McBSP Receive Buffer Threshold Register DMA or IRQ trigger THRSH1_REG The McBSP_THRSH1_REG register is shown in Figure 11 68 and described in Ta...

Page 1203: ...to 1 when the transmit data buffer is empty new data is required to be transmitted 0 The transmit data buffer is NOT empty new data is required to be transmitted 1 The transmit data buffer is empty ne...

Page 1204: ...ions are equal or above the THRSH1_REG value 0 Receive buffer occupied locations are below the THRSH1_REG value 1 Receive buffer occupied locations are equal or above the THRSH1_REG value Writing 1 to...

Page 1205: ...rflow NOT enabled 1 Transmit Buffer Overflow enabled 11 XUNDFLEN Transmit Buffer Underflow enable bit 0 Transmit Buffer Underflow NOT enabled 1 Transmit Buffer Underflow enabled 10 XRDYEN Transmit Buf...

Page 1206: ...eceive End Of Frame NOT enabled 1 Receive End Of Frame enabled 1 RFSREN Receive Frame Synchronization enable bit 0 Receive Frame Synchronization NOT enabled 1 Receive Frame Synchronization enabled 0 R...

Page 1207: ...f Frame WK enable is NOT active 1 Transmit End Of Frame WK enable is active 8 XFSXEN Transmit Frame Synchronization WK enable bit 0 Transmit Frame Synchronization WK enable is NOT active 1 Transmit Fr...

Page 1208: ...data into the receive buffer 0 External clock gating disabled 1 External clock gating enable 14 PPCONNECT Pair to pair connection When set the DXENO pin is always set to 0 regardless of the frame bou...

Page 1209: ...McBSP_RCCR_REG Field Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved 11 RFULL_CYCLE Receive full cycle mode select 0 McBSP module operates in receive half cycle mode receive frame s...

Page 1210: ...and it can be smaller than the real number of the free locations which are seen by the transmit state machine Figure 11 75 McBSP_XBUFFSTAT_REG 31 11 10 0 Reserved XBUFFSTAT R 0 R 500h LEGEND R Read on...

Page 1211: ...it can be smaller than the real number of the occupied locations which are seen by the receive state machine Figure 11 77 McBSP_RBUFFSTAT_REG 31 11 10 0 Reserved RBUFFSTAT R 0 R 0 LEGEND R Read only...

Page 1212: ...d 0 CLKMUXSTATUS Indicates that the McBSP AUDIOBUFFER clock muxing is done after exiting SmartIdle mode When this bit is set one the response to a different register access is delayed until the muxing...

Page 1213: ...This chapter describes the multichannel serial port interface McSPI module Topic Page 12 1 Introduction 1214 12 2 Architecture 1215 12 3 Registers 1251 1213 SPRUGX9 15 April 2011 Multichannel Serial P...

Page 1214: ...ommunication between a CPU and SPI compliant external devices Slaves and Masters Figure 12 1 shows a high level overview of a SPI system Figure 12 1 System Overview 12 1 2 Features The McSPI includes...

Page 1215: ...utput MOSI or MISO SPI_CS0 I O SPI chip select 0 output when master input when slave active low SPI_CS1 I O SPI chip select 0 output when master input when slave active low SPI_CS2 I O SPI chip select...

Page 1216: ...AT 1 0 Each time a bit is transferred out from the Master one bit is transferred in from Slave Figure 12 2 shows an example of a full duplex system with a Master device on the left and a Slave device...

Page 1217: ...ter device on the left and a receive only Slave device on the right Each time a bit is transferred out from the Master one bit is transferred in the Slave After 8 cycles of the serial clock SPICLK the...

Page 1218: ...tory Only a single master of slave device can be connected to the SPI bus 12 2 2 3 3 Programmable SPI Enable SPIEN The polarity of the SPIEN signals is programmable SPIEN signals can be active high or...

Page 1219: ...for two different slave devices may go along with active SPICLK signal with different phase and polarity Table 12 2 Phase and Polarity Combinations Polarity POL Phase PHA SPI Mode Comments 0 0 mode0 S...

Page 1220: ...ansmitted on the serial data line This process continues for a total of pulses on the SPICLK line defined by the SPI word length programmed in the master device with data being latched on odd numbered...

Page 1221: ...he third edge occurs the received data bit is shifted into the shift register The next data bit of the master is provided to the serial input pin of the slave This process continues for a total of pul...

Page 1222: ...TRM Interface mode Two data pins or Single data pin and data pins assignment both programmable with the bits IS and DPE SPI word length programmable with the bits WL SPIEN polarity programmable with t...

Page 1223: ...must be loaded seldom TX_underflow interrupt status bit must be cleared for interrupt line de assertion if event enable as interrupt source Note Be careful when more than one channel have a FIFO enabl...

Page 1224: ...r this channel The serialization transmit and receive starts according to the channel communication configuration On serialization completion the received data is transferred to the channel receive re...

Page 1225: ...s soon as transmit register or FIFO is not empty In 4 pin mode MCSPI_MODULCTRL 1 PIN34 bit is cleared to 0 and MCSPI_MODULCTRL 0 SINGLE bit is set to 1 SPIEN assertion deassertion controlled by Softwa...

Page 1226: ...be modified when the SPIEN signal is activated The Transmit Receive mode programmable with the bit TRM can be modified only when the channel is disabled The channel can be disabled and enabled while t...

Page 1227: ...XS of the register MCSPI_CH I STAT at the time of shift register assignment until the shift register is full The receiver register cannot be overwritten in turbo mode In consequence the RX_overflow bi...

Page 1228: ...9 10 11 12 13 14 15 16 17 18 D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB Transfer Preliminary Architecture www ti com Figure 12 10 Extended SPI Transfer With...

Page 1229: ...ck divider ratio which occurs when granularity is one clock cycle that means that MCSPI_CH I CONF CLKG is set to 1 and MCSPI_CH I CONF CLKD has an even value the clock duty cycle is not 50 then one of...

Page 1230: ...Architecture www ti com Fratio MCSPI_CH I CNTRL EXTCLK MCSPI_CH I CONF CLKD 1 1230 Multichannel Serial Port Interface McSPI SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments I...

Page 1231: ...Fratio 2 T_ref CLKSPIREF period in ns Thigh_ref CLKSPIREF high Time period in ns Tlow_ref CLKSPIREF low Time period in ns Fratio SPI clock division ratio Fratio MCSPI_CH I CTRL EXTCLK MCSPI_CH I CONF...

Page 1232: ...y Receive only or Transmit Receive mode Single channel or turbo mode or in normal round robin mode In round robin mode the buffer is used by only one channel Every word length MCSPI_CH I CONF WL are s...

Page 1233: ...X Shift Register RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 0x0 Transmit receive mode MCSPI_CH i CONF FFRE 0x1 FIFO enabled on receive path...

Page 1234: ...r RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 0x0 Transmit receive mode MCSPI_CH i CONF FFRE 0x1 FIFO enabled on receive path MCSPI_CH i CON...

Page 1235: ...FNBYTE Depth TX Shift Register RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 012 Receive only mode MCSPI_CH i CONF FFRE 0x1 FIFO enabled on re...

Page 1236: ...this level an interrupt or a DMA request is sent to the CPU to enable system to read AFL 1 bytes from receive register Be careful AFL 1 must correspond to a multiple value of MCSPI_CH I CONF WL When D...

Page 1237: ...write accesses Figure 12 19 Buffer Almost Empty Level AEL 12 2 3 10 4 End of Transfer Management When the FIFO buffer is enabled for a channel the user shall previously configure the MCSPI_XFERLEVEL...

Page 1238: ...mber of SPI word access depending on SPI word length 3 WL 7 SPI word length smaller or equal to byte length four SPI words accessed per 32 bit OCP read write If word count is used MCSPI_XFERLEVEL WCNT...

Page 1239: ...eared to 0 default value the controller is in 4 pin mode using the SPI pins CLKSPI SOMI SIMO and chip enable CS If MCSPI_MODULECTRL 34 is set to 1 the controller is in 3 pin mode using the SPI pins CL...

Page 1240: ...in shift register whether it has been updated or not The transmitter register should be loaded before McSPI is selected by a master Its own receiver register MCSPI_RX on top of the common shift regist...

Page 1241: ...is enabled and its transmitter register becomes empty Enabling channel automatically raises this event When FIFO buffer is enabled MCSPI_CH I CONF FFEW set to 1 the TX_empty is asserted as soon as th...

Page 1242: ...n slave mode in either transmit and receive or receive only mode when a channel is enabled and the SPI_RXn register or FIFO is full when a new SPI word is received The SPI_RXn register is always overw...

Page 1243: ...he Transmitter register should be loaded before McSPI is selected by an external SPI master device Transmitter register or FIFO if use of buffer enabled content is always loaded in shift register whet...

Page 1244: ...register then the FIFO is seen as a unique FFNBYTE bytes buffer Figure 12 24 shows a half duplex system with a master device on the left and a transmit only slave device on the right Each time a bit t...

Page 1245: ...derflow and RX_overflow Writing a 1 into the corresponding bit of MCSPI_IRQSTATUS register clears the interrupt status and does not affect the interrupt line state 12 2 6 DMA Requests McSPI can be int...

Page 1246: ...an enabled channel which manages the FIFO to be compliant the a DMA handler providing only 256 bit aligned addresses This features is activated when the bit field MCSPI_MODULCTRL 8 FDAA is set to 1 an...

Page 1247: ...ode force idle mode and smart idle mode When programmed for no idle mode the bit SIdleMode of the register MCSPI_SYSCONFIG is set to 01 the module ignores the system power manager request and behaves...

Page 1248: ...e idle mode the module is supposed to be disabled at that time so the interrupt and DMA request lines are likely deasserted OCP clock and SPI clock provided to McSPI can be switched off An idle reques...

Page 1249: ...iver or transmitter and does not support successive 8 bit or 16 bit accesses for a single SPI word The SPI word received is always right justified on LSbit of the 32bit register MCSPI_RX i and the SPI...

Page 1250: ...channel Write 0000 0001h in MCSPI_CH i CTRL First write request TX empty Generate DMA write event polling TX empty flag by CPU to write First transmit word into MCSPI_TX i End of transfer Stop the cha...

Page 1251: ...T McSPI channel i status register Section 12 3 8 148h MCSPI_CH1CTRL McSPI channel n control register Section 12 3 9 14Ch MCSPI_TX1 McSPI channel i FIFO transmit buffer register Section 12 3 10 150h MC...

Page 1252: ...itched off 2h Functional clock is maintained OCP clock may be switched off 3h OCP and Functional clocks are maintained 7 5 Reserved 0 Reads returns 0 4 3 SIDLEMODE Power management 0 If an idle reques...

Page 1253: ...s Register MCSPI_SYSSTATUS 31 16 Reserved R 0 15 1 0 Reserved RESETDONE R 0 R 0 LEGEND R Read only n value after reset Table 12 9 McSPI System Status Register MCSPI_SYSSTATUS Field Descriptions Bit Fi...

Page 1254: ...count event when a channel is enabled using the FIFO buffer and the channel has sent the number of McSPI words defined by the MCSPI_XFERLEVEL WCNT Write 0 Event status bit is unchanged Read 0 Event f...

Page 1255: ...us when built in FIFO is used for transmit register MCSPI_CH3CONF FFE2W is set Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bit is reset Read 1 Event is pending 7 Rese...

Page 1256: ...Transmitter register underflow Channel 0 Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bit is reset Read 1 Event is pending 0 TX0_EMPTY Transmitter register empty or a...

Page 1257: ...17 EOWKE End of word count interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 16 Reserved Reserved 15 Reserved 0 Reads return 0 14 RX3_FULL_ ENABLE MCSPI_RX3 receiver register full or al...

Page 1258: ...rrupt is disabled 1 Interrupt is enabled 3 RX0_OVERFLOW_ ENABLE MCSPI_RX0 receivier register overflow interrupt enable channel 0 0 Interrupt is disabled 1 Interrupt is enabled 2 RX0_FULL_ ENABLE MCSPI...

Page 1259: ...tained in the MCSPI_IRQSTATUS register 10 SPIENDIR Sets the direction of the SPIEN 3 0 lines and SPICLK line 0 Output as in master mode 1 Input as in slave mode 9 SPIDATDIR1 Sets the direction of the...

Page 1260: ...n this bit returns the value on the SPIEN 2 line high or low and a write into this bit has no effect 1 SPIEN_1 SPIEN 1 line signal data value If MCSPI_SYST SPIENDIR 0 output mode direction the SPIENT...

Page 1261: ...m to perform multiple SPI word access for a single 32 bit OCP word access This is possible for WL 16 0 Multiple word access disabled 1 Multiple word access enabled with FIFO 6 4 INITDLY Initial SPI de...

Page 1262: ...scription 0 SINGLE Single channel Multi Channel master mode only 0 More than one channel will be used in master mode 1 Only one channel will be used in master mode This bit must be set in Force SPIEN...

Page 1263: ...RL EXTCLK must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF CLKD and MCSPI_CHCTRL EXTCLK values 0 Clock granularity of p...

Page 1264: ...line 1 SPIDAT 1 selected for reception 17 DPE1 Transmission enable for data line 1 SPIDATAGZEN 1 0 Data line 1 SPIDAT 1 selected for transmission 1 No transmission on data line 1 SPIDAT 1 16 DPE0 Tran...

Page 1265: ...e SPI word is 16 bits long 10h The SPI word is 17 bits long 11h The SPI word is 18 bits long 12h The SPI word is 19 bits long 13h The SPI word is 20 bits long 14h The SPI word is 21 bits long 15h The...

Page 1266: ...8 4h 16 5h 32 6h 64 7h 128 8h 256 9h 512 Ah 1024 Bh 2048 Ch 4096 Dh 8192 Eh 16384 Fh 32768 1 POL SPICLK polarity 0 SPICLK is held high during the active state 1 SPICLK is held low during the active st...

Page 1267: ...hannel i FIFO transmit buffer empty status 0 FIFO transmit buffer is not empty 1 FIFO transmit buffer is empty 2 EOT Channel i end of transfer status The definitions of beginning and end of transfer v...

Page 1268: ...ister MCSPI_CH I CTRL Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8 EXTCLK Clock ratio extension Used to concatenate with the CLKD bit field in MCSPI_CHnCONF for clock...

Page 1269: ...d Value Description 31 0 TDATA 0 FFFF FFFFh Channel i data to transmit 12 3 11 McSPI Channel i Receive Register MCSPI_RX i The McSPI channel i FIFO receive buffer register MCSPI_RX i contains a single...

Page 1270: ...ter returns the current SPI word transfer index 0 Counter not used 1 1 SPI word FFFEh 65534 SPI word FFFFh 65535 SPI word 15 8 AFL Buffer almost full Holds the programmable almost full level value use...

Page 1271: ...CIESS provides a high speed glueless serial interconnect to peripherals utilizing high bandwidth applications Topic Page 13 1 Introduction 1272 13 2 Architecture 1276 13 3 Use Case 1303 13 4 Registers...

Page 1272: ...system It is designed to replace the PCI based shared parallel bus signaling technology that is approaching its practical performance limits while simplifying the interface design It includes cost pe...

Page 1273: ...egacy Endpoint or native PCIe Endpoint The role it assumes is based on the state of the PCIe Configuration register within the Control Module bit field PCIE_DEVTYPE PCIE_CFG DEVTYPE 00b 01b 10b EP Leg...

Page 1274: ...is generated from the internal PLL and should be programmed to generate a clock frequency of 250MHz The PCIESS supports the Conventional Reset mechanism that is specified within the PCI Express Speci...

Page 1275: ...mplies with the following standards Revision 2 0 of the PCI Express Base Specification Synopsys DWC PCIe Dual Core Version 3 51a TI SERDES 1 1 03 13 1 7 Terminology Used in this Document Term Definiti...

Page 1276: ...to verify lock status 13 2 2 Supported PCIe Transactions All of the PCIe Transactions defined Posted and Non Posted are supported except the Locked Memory Read request transaction and its subsequent c...

Page 1277: ...s range is divided into 32 equally sized translation regions Regions 0 to 31 These equally divided regions can be programmed to have a size of 1 2 4 or 8 MB and this size value is communicated with th...

Page 1278: ...of 9D3A_1234h what would be the corresponding PCIe Address that would be used on an outgoing TLP Header assume a 2MB region partition For this example further assume the followings 64 bit addressing i...

Page 1279: ...cated for local application registers local configuration accesses remote configuration accesses and remote IO accesses RC only The second address space Address Space One also known as region 1 is ded...

Page 1280: ...RC programmed addresses Further assume that application software has programmed the set of registers corresponding to Region 1 with the values shown below IB_BAR1 2 This assignment associates Region 1...

Page 1281: ...l capability of using the value of BAR1 register from PCIe Configuration Space as the start address for inbound address translation This feature can be activated by leaving the start address of the co...

Page 1282: ...data transfer size is controlled 13 2 3 5 Zero Length Read Write Transactions Read transactions that request zero bytes are not supported by PCIESS PCIESS will read issue a read with FBE field of PCI...

Page 1283: ...emote Configuration Registers 4 PCIe IO Access Window Figure 13 3 illustrates the relationship of the various address regions within the Address Space Zero Figure 13 3 Address Space Zero Relationships...

Page 1284: ...The BAR values setup within the PCIe Local Configuration Registers define where within the memory map of the CPU on Root Complex side are the End Points located All locations other than what is setup...

Page 1285: ...k state of the other device The Loopback entry procedure when PCIESS is a Loopback Slave If the PCIESS is a Loopback slave then the incoming serial data is routed back to the originating device from t...

Page 1286: ...lock within L3 region with starting address of 5100_0000h and ending address of 51FF FFFFh This address region is referred to Address Space Zero within PCIe Two more additional registers within the Co...

Page 1287: ...640h and the register format and description are shown in Figure 13 4 and Table 13 4 The PCIE_CFG register is used to configure the PCIe role to be in RC or EP mode It is also used to configure the P...

Page 1288: ...converter mismatch on Ch 1 6 4 TESTPATT1 PCIe Ch1 Test Pattern Select 0 GWR R W R NA 000 Test Mode disabled 001 Alternating 0 1 pattern 010 PRBS 7 bit LFSR x7 x6 1 feedback 011 PRBS 23 bit LFSR x23 x...

Page 1289: ...0 7 PCI_LRST ACTIVE domain PCI Local reset control 0 Reset is cleared for the DEFAULT domain Security SS local M3 1 Reset is asserted for the DEFAULT domain Security SS local M3 6 5 Reserved 3h Reser...

Page 1290: ...te 1 to clear n value after reset Table 13 7 RM_DEFAULT_RSTST Register Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 PCI_LRST PCI local software reset 0 No software reset o...

Page 1291: ...RCTRL R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 13 8 CM_DEFAULT_PCI_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Read returns 0 8 CLKAC...

Page 1292: ...dule is fully functional including OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock...

Page 1293: ...our interrupt events are supported by the PCIESS Some of the events are meaningful based on the role the PCIESS assumes RC or EP Table 13 10 captures the Interrupt events supported for both RC and EP...

Page 1294: ..._CLR register to disable the legacy interrupt by sending a DEASSERT INT A B C D message Once an assert message has been generated it cannot be generated again until a deassert message is generated Thu...

Page 1295: ...or Legacy EP For this reason it should be able to handle both MSI and Legacy Interrupt 13 2 9 3 2 1 MSI Interrupt Reception in RC Mode A total of 32 MSI interrupts can be generated from one or more d...

Page 1296: ...e PCIESS is generating a request it means that an external PCIe component is the actual entity generating the request and the PCIESS is now regarded as a Master If the PCIESS is accessing external PCI...

Page 1297: ...rate for each of these transactions will be about 85 of 2 Gbps 4Gbps in Gen2 mode in each direction on each PCIe lane 1297 SPRUGX9 15 April 2011 Peripheral Component Interconnect Express PCIe Submit D...

Page 1298: ...1 Power State Support for D1 state is optional and is primarily driven by software It is considered to be a light sleep state that provides some power savings compared to D0 state while still allowing...

Page 1299: ...ired beyond writing the Power State bits If the internal reset is performed devices return to D0 Un initialized and a full re initialization is performed on the device The full re initialization seque...

Page 1300: ...riate when a device needs to monitor an external event while in deep power down mode In L2 state auxiliary power is supplied and a minimal amount of current is drawn from the power source Almost all o...

Page 1301: ...Preliminary www ti com Architecture 1301 SPRUGX9 15 April 2011 Peripheral Component Interconnect Express PCIe Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1302: ...tions L0 L1 L1 L0 SMART STANDBY SMART IDLE WITH WAKE States L0 L1 The valid transitions among these states are tested Transitions L0 L1 L1 L0 L0 L2 L3 Ready The states L2 and L3 need fundamental reset...

Page 1303: ...rted on various end points 13 3 1 2 Configuration Accesses Configuration accesses are made by RC port to individual function in each downstream EP device to program the PCIe specific operating paramet...

Page 1304: ...peration for EP Mode by programming PCIE_CFG PCIE_DEVTYPE with a value of 0 2 Bring PCIESS out of reset through the device level reset controller 3 Enable and configure PCIe Clock See PCIE_CFG Registe...

Page 1305: ...ansaction over the PCIE link Once the PCIESS receives completion from the remote device it generates a completion on the OCP slave port The software hardware that initiates the request on the slave po...

Page 1306: ...CT 2h POLLACTIVE 3h POLLCOMPLIANCE 4h POLLCONFIG 5h PREDETECTQUIET 6h DETECTWAIT 7h CFGLINKWDSTART 8h CFGLINKWDACEPT 9h CFGLANENUMWAIT Ah CFGLANENUMACEPT Bh CFGCOMPLETE Ch CFGIDLE Dh RCVRYLOCK Eh RCVR...

Page 1307: ...STATUS Section 13 4 4 2 8h CFG_SETUP Section 13 4 4 3 Ch IOBASE Section 13 4 4 4 10h TLPCFG Section 13 4 4 5 14h RSTCMD Section 13 4 4 6 20h PMCMD Section 13 4 4 7 24h PMCFG Section 13 4 4 8 28h ACT_S...

Page 1308: ...RT1_LO Section 13 4 4 46 318h IB_START1_HI Section 13 4 4 47 31Ch IB_OFFSET1 Section 13 4 4 48 320h IB_BAR2 Section 13 4 4 49 324h IB_START2_LO Section 13 4 4 50 328h IB_START2_HI Section 13 4 4 51 32...

Page 1309: ...ly n value after reset Table 13 16 PID Register Field Descriptions Bit Field Value Description 31 30 SCHEME 0 3h PID Register Format Scheme 29 28 Reserved 0 Reserved 27 16 FUNC 0 FFFh Function code of...

Page 1310: ...e Setting this bit will enable all incoming PCIe transactions to be returned with a retry response This feature can be used if initialization can take longer than PCIe stipulated time frame 3 POSTED_W...

Page 1311: ...S 0 FFh PCIe Bus number for outbound configuration accesses 15 13 Reserved 0 Reserved 12 8 CFG_DEVICE 0 1Fh PCIe Device number for outbound configuration accesses 7 3 Reserved 0 Reserved 2 0 CFG_FUNC...

Page 1312: ...ter RSTCMD is described in the table and figure below Figure 13 18 RSTCMD Register 31 17 16 Reserved FLUSH_N R 0 R 1 15 1 0 Reserved INIT_RST R 0 W1S 0 LEGEND R Read only W1S Write 1 to set n value af...

Page 1313: ...mit a PM_PME message Reads zero Applicable to EP mode only 13 4 4 8 PMCFG Register The power management configuration register PMCFG is described in the figure and table below Figure 13 20 PMCFG Regis...

Page 1314: ...EMPTY 0 Inbound buffers are empty if this bit is read as 1 13 4 4 10 OB_SIZE Register The outbound size register OB_SIZE is described in the figure and table below Figure 13 22 OB_SIZE Register 31 16...

Page 1315: ...injected on one TLP 0 INV_LCRC 0 Write 1 to force inversion of LSB of LCRC for next one packet It is self cleared when the ECRC error has been injected on one TLP 13 4 4 12 ENDIAN Register The endian...

Page 1316: ...erved 1 0 MST_PRIORITY 0 3h Priority level for each inbound transaction on the CBA master port This field is not used for OCP interface 13 4 4 14 IRQ_EOI Register The end of interrupt register IRQ_EOI...

Page 1317: ...se on bit 0 triggering the MSI interrupt from PCIESS to the external processor 13 4 4 16 EP_IRQ_SET Register The endpoint interrupt request set register EP_IRQ_SET is described in the figure and table...

Page 1318: ...MSI is disabled legacy interrupt deassert message will be generated On read a 1 indicates currently asserted 13 4 4 18 EP_IRQ_STATUS Register The endpoint interrupt status register EP_IRQ_STATUS is d...

Page 1319: ...13 32 GPR1 Register 31 0 GENERIC1 R W 0 LEGEND R W Read Write n value after reset Table 13 35 GPR1 Register Field Descriptions Bit Field Value Description 31 0 GENERIC1 0 FFFF FFFFh Generic Info field...

Page 1320: ...Field Value Description 31 0 MSI0_RAW_STATUS 0 FFFF FFFFh Each bit indicates raw status of MSI vector associated with the bit Typically writes to this register are only done for debug purposes 13 4 4...

Page 1321: ...es the MSI interrupt associated with the bit 13 4 4 26 MSI0_IRQ_ENABLE_CLR Register The MSI0 interrupt enable clear register MSI0_IRQ_ENABLE_SET is described in the figure and table below Figure 13 38...

Page 1322: ...described in the figure and table below Figure 13 40 IRQ_STATUS Register 31 8 Reserved R 0 7 4 3 2 1 0 Reserved INTD INTC INTB INTA R 0 R W0C 0 R W0C 0 R W0C 0 R W0C 0 LEGEND R W Read Write R Read onl...

Page 1323: ...e zero means interrupt is enabled disabled 13 4 4 30 IRQ_ENABLE_CLR Register The interrupt enable clear register IRQ_ENABLE_CLR is described in the figure and table below Figure 13 42 IRQ_ENABLE_CLR R...

Page 1324: ...ror FATAL NONFATAL or CORRECTABLE error raw status 13 4 4 32 ERR_IRQ_STATUS Register The ERR interrupt enabled status register ERR_IRQ_STATUS is described in the figure and table below Figure 13 44 ER...

Page 1325: ...Set to enable On read 1 0 means enabled disabled respectively 4 ERR_AXI 0 AXI tag lookup fatal error interrupt enable Set to enable On read 1 0 means enabled disabled respectively 3 ERR_CORR 0 Correc...

Page 1326: ...t to disable On read 1 0 means enabled disabled respectively 4 ERR_AXI 0 AXI tag lookup fatal error interrupt disable Set to disable On read 1 0 means enabled disabled respectively 3 ERR_CORR 0 Correc...

Page 1327: ...er Management Turnoff message received raw status 13 4 4 36 PMRST_IRQ_STATUS Register The power management and reset interrupt enabled status register PMRST_IRQ_STATUS is described in the figure and t...

Page 1328: ...errupt Read 1 means interrupt is enabled 13 4 4 38 PMRST_ENABLE_CLR Register The power management and reset interrupt enabled clear register PMRST_ENABLE_CLR is described in the figure and table below...

Page 1329: ...et bits 31 20 for translation region N N 0 31 19 1 Reserved 0 Reserved 0 OB_ENABLEn 0 Enable translation region N N 0 31 13 4 4 40 OB_OFFSETn_HI Register The outbound translation region N offset high...

Page 1330: ...0 15 3 2 0 Reserved IB_BAR0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 13 56 IB_BAR0 Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 IB_...

Page 1331: ...its 31 8 for inbound translation region 0 7 0 Reserved 0 Reserved 13 4 4 43 IB_START0_HI Register The inbound translation 0 start address high register IB_START0_HI is described in the figure and tabl...

Page 1332: ...inbound translation region 0 7 0 Reserved 0 Reserved 13 4 4 45 IB_BAR1 Register The inbound translation bar match 1 register IB_BAR1 is described in the figure and table below Figure 13 57 IB_BAR1 Re...

Page 1333: ...its 31 8 for inbound translation region 1 7 0 Reserved 0 Reserved 13 4 4 47 IB_START1_HI Register The inbound translation 1 start address high register IB_START1_HI is described in the figure and tabl...

Page 1334: ...r inbound translation region 1 7 0 Reserved 0 Reserved 13 4 4 49 IB_BAR2 Register The inbound translation bar match 2 register IB_BAR2 is described in the figure and table below Figure 13 61 IB_BAR2 R...

Page 1335: ...its 31 8 for inbound translation region 2 7 0 Reserved 0 Reserved 13 4 4 51 IB_START2_HI Register The inbound translation 2 start address low register B_START2_HI is described in the figure and table...

Page 1336: ...r inbound translation region 2 7 0 Reserved 0 Reserved 13 4 4 53 IB_BAR3 Register The inbound translation bar match 3 register B_BAR3 is described in the figure and table below Figure 13 65 IB_BAR3 Re...

Page 1337: ...its 31 8 for inbound translation region 3 7 0 Reserved 0 Reserved 13 4 4 55 IB_START3_HI Register The inbound translation 3 start address high register IB_START3_HI is described in the figure and tabl...

Page 1338: ...FSET3 R W 0 7 0 Reserved R 0 LEGEND R W Read Write R Read only n value after reset Table 13 71 IB_OFFSET3 Register Field Descriptions Bit Field Value Description 31 8 IB_OFFSET3 0 FF FFFFh Offset addr...

Page 1339: ...31 29 Reserved 0 Reserved 28 24 PCS_SYNC 0 1Fh Receiver Lock Sync Control 23 16 PCS_HOLDOFF 0 FFh Receiver Initialization Hold Off Control 15 14 Reserved 0 Reserved 13 12 PCS_RC_DELAY 0 3h Rate Chang...

Page 1340: ...e 13 4 4 59 PCS_STATUS Register The PCS status register is described in the figure and table below Figure 13 71 PCS_STATUS Register 31 16 Reserved R 0 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsvd PCS_REV R...

Page 1341: ...igh to enable CFGTX0 28 27 18 TX_MSYNC 0 Master mode for synchronization CFGTX0 22 17 TX_CM 0 Enable common mode adjustment CFGTX0 8 16 TX_INVPAIR 0 Invert TX pair polarity CFGTX0 7 15 14 RX_LOOPBACK...

Page 1342: ...gh to enable CFGTX1 28 27 18 TX_MSYNC 0 Master mode for synchronization CFGTX1 22 17 TX_CM 0 Enable common mode adjustment CFGTX1 8 16 TX_INVPAIR 0 Invert TX pair polarity CFGTX1 7 15 14 RX_LOOPBACK 0...

Page 1343: ...ter VENDOR_DEVICE_ID is described in the figure and table below Figure 13 74 VENDOR_DEVICE_ID Register 31 16 device_id R 8888h 15 0 vendor_id R 104Ch LEGEND R W Read Write R Read only n value after re...

Page 1344: ...ng as a Completer terminates a request by issuing Completer Abort Abort Completion Status to the Requester 26 25 Reserved 0 Reserved 24 Data Parity Error 0 This bit is set by a Requester if the Parity...

Page 1345: ...n value after reset Table 13 80 CLASSCODE_REVID Register Field Descriptions Bit Field Value Description 31 8 Class Code 0 FF FFFFh PCIe Class Code per PCIe Base Specifications Revision 2 0 Writable fr...

Page 1346: ...Header Type BIST Device R 0 R 0 R 0 R 0 R 0 R 0 15 8 7 0 Latency Timer Cache Line Size R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 13 82 BIST_HEADER Register Field Descripti...

Page 1347: ...iption 31 7 Base Address 0 1FF FFFFh Base Address 6 4 Reserved 0 Reserved 3 Prefetchable 0 For memory BARs it indicates whether the region is prefetchable For IO Bars it is used as second LSB of the b...

Page 1348: ...rs it is used as second LSB of the base address Writable from internal bus interface 2 1 Type 0 3h Decode type Writable from internal bus interface 0 32 bit decode 1h Reserved 2h 64 bit decode 3h Rese...

Page 1349: ...iption 31 7 Base Address 0 1FF FFFFh Base Address 6 4 Reserved 0 Reserved 3 Prefetchable 0 For memory BARs it indicates whether the region is prefetchable For IO Bars it is used as second LSB of the b...

Page 1350: ...rs it is used as second LSB of the base address Writable from internal bus interface 2 1 Type 0 3h Decode type Writable from internal bus interface 0 32 bit decode 1h Reserved 2h 64 bit decode 3h Rese...

Page 1351: ...iption 31 7 Base Address 0 1FF FFFFh Base Address 6 4 Reserved 0 Reserved 3 Prefetchable 0 For memory BARs it indicates whether the region is prefetchable For IO Bars it is used as second LSB of the b...

Page 1352: ...rs it is used as second LSB of the base address Writable from internal bus interface 2 1 Type 0 3h Decode type Writable from internal bus interface 0 32 bit decode 1h Reserved 2h 64 bit decode 3h Rese...

Page 1353: ...Vendor ID TBD Writable from internal bus interface 13 4 6 9 EXPNSN_ROM Register The expansion ROM base address EXPNSN_ROM is described in the figure and table below Figure 13 88 EXPNSN_ROM Register 3...

Page 1354: ..._PIN Register 31 24 23 16 max_latency min_grant R 0 R 0 15 8 7 0 int_pin int_line R 1 R W FFh LEGEND R W Read Write R Read only n value after reset Table 13 95 INT_PIN Register Field Descriptions Bit...

Page 1355: ...art Reserved Completion Code Multi function Header Type BIST Device R 0 R 0 R 0 R 0 R 0 R 1 15 8 7 0 Latency Timer Cache Line Size R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table...

Page 1356: ...served 0 Memory Space 0 Set to indicate Memory Space Writable from internal bus interface 13 4 7 3 BAR1 Register Figure 13 93 BAR1 Register 31 8 Base Address R 0 7 4 3 2 1 0 Base Address Prefetchable...

Page 1357: ...ster 31 24 23 16 Secondary Latency Timer Subordinate Bus Number R 0 R W 0 15 8 7 0 Secondary Bus Number Primary Bus Number R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 13 10...

Page 1358: ...Description 31 DTCT_PERROR 0 Detected Parity Error 30 RX_SYS_ERROR 0 Received System Error 29 RX_MST_ABORT 0 Received Master Abort 28 RX_TGT_ABORT 0 Received Target Abort 27 TX_TGT_ABORT 0 Signaled Ta...

Page 1359: ...M Register 31 20 19 17 16 End Address Reserved Memory Addressing R W 0 R 0 R 0 15 4 3 1 0 Start Address Reserved Memory Addressing R W 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset T...

Page 1360: ...egister 31 0 Base Address R W 0 LEGEND R W Read Write n value after reset Table 13 106 PREFETCH_LIMIT Register Field Descriptions Bit Field Value Description 31 0 Limit Address 0 FFFF FFFFh Upper 32 b...

Page 1361: ...interface 13 4 7 12 EXPNSN_ROM Register The expansion ROM base address register EXPNSN_ROM is described in the figure and table below Figure 13 103 EXPNSN_ROM Register 31 16 Expansion ROM Base Address...

Page 1362: ...Discard Timer Not applicable to PCI Express 24 PRI_TIMER 0 Primary Discard Timer Not applicable to PCI Express 23 B2B_EN 0 Fast Back to Back Transactions Enable Not applicable to PCI Express 22 SEC_BU...

Page 1363: ...1 30 29 25 24 23 20 19 16 Reserved INT_MSG SLT_IMPL_N DPORT_TYPE PCIE_CAP R 0 R 0 R 0 R x R 2h 15 8 7 0 NEXT_CAP CAP_ID R 0 R 10h LEGEND R Read only n value after reset Table 13 112 PCIE_CAP Register...

Page 1364: ...mit Scale 25 18 PWR_LIMIT_VALUE 0 FFh Captured Slow Power Limit Value 17 16 Reserved 0 Reserved 15 ERR_RPT 0 Role based Error Reporting Writable from internal bus interface 14 12 Reserved 0 Reserved 1...

Page 1365: ...ed 21 TPEND 0 Transaction Pending 20 AUX_PWR 0 Auxiliary Power Detected 19 UNSUP_RQ_DET 0 Unsupported Request Detected 18 FATAL_ERR 0 Fatal Error Detected 17 NFATAL_ERR 0 Non fatal Error Detected 16 C...

Page 1366: ...EP_CAP 0 Data Link Layer Active Reporting Capable Always 1 for downstream and 0 for upstream 19 DOWN_ERR_REP_CAP 0 Surprise Down Error Reporting Capable Not supported Always zero 18 CLK_PWR_MGMT 0 Clo...

Page 1367: ...e from internal bus interface 27 LINK_TRAINING 0 Link Training Not applicable to Root Complex 26 UNDEF 0 Undefined for PCI Express 25 20 NEGOTIATED_LINK_WD 0 3Fh Negotiated Link Width Set automaticall...

Page 1368: ...16 15 PWR_LMT_SCALE 0 3h Slow Power Limit Scale Writable from internal bus interface 14 7 PWR_LMT_VALUE 0 FFh Slow Power Limit Value Writable from internal bus interface 6 HP_CAP 0 Hot Plug Capable W...

Page 1369: ...23 EM_LOCK 0 Electromechanical Lock Status 22 PRESENCE_DET 0 Presence Detect State 21 MRL_STATE 0 MRL Sensor State 20 CMD_COMLETE 0 Command Completed 19 PRESENCE_CHG 0 Presence Detect Changed 18 MRL_C...

Page 1370: ...NT_EN 0 PME Interrupt Enable 2 SERR_FATAL_ERR 0 System Error on Fatal Error Enable 1 SERR_NFATAL_ERR 0 System Error on Non fatal Error Enable 0 SERR_EN 0 System Error on Correctable Error Enable 13 4...

Page 1371: ..._EN 0 Fh Completion timeout ranges supported Applicable to RC EP 13 4 8 11 DEV_STAT_CTRL2 Register Figure 13 115 DEV_STAT_CTRL2 Register 31 5 Reserved R 0 15 5 4 3 0 Reserved CMPL_TO_DIS CMPL_TO R 0 R...

Page 1372: ...scription 31 17 Reserved 0 Reserved 16 DE_EMPH 0 Current De emphasis level 15 13 Reserved 0 Reserved 12 POLL_DEEMPH 0 DE emphasis level in polling compliance state 11 CMPL_SOS 0 Compliance SOS 10 ENTR...

Page 1373: ...on 13 4 9 10 128h HDR_LOG3 Section 13 4 9 11 12Ch RC_ERR_CMD Section 13 4 9 12 130h RC_ERR_ST Section 13 4 9 13 134h ERR_SRC_ID Section 13 4 9 14 13 4 9 1 PCIE_EXTCAP Register Figure 13 117 PCIE_EXTCA...

Page 1374: ...ld Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 UR_ERR_ST 0 Unsupported Request Error Status 19 ECRC_ERR_ST 0 ECRC Error Status 18 MTLP_ERR_ST 0 Malformed TLP Status 17 RCVR_O...

Page 1375: ...Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 UR_ERR_MSK 0 Unsupported Request Error Mask 19 ECRC_ERR_MSK 0 ECRC Error Mask 18 MTLP_ERR_MSK 0 Malformed TLP Mask 17 RCVR_OF_MSK...

Page 1376: ...eld Value Description 31 21 Reserved 0 Reserved 20 UR_ERR_SVRTY 0 Unsupported Request Error Severity 19 ECRC_ERR_SVRTY 0 ECRC Error Severity 18 MTLP_ERR_SVRTY 1 Malformed TLP Severity 17 RCVR_OF_SVRTY...

Page 1377: ...to clear n value after reset Table 13 129 PCIE_CERR Register Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved 13 ADV_NFERR_ST 0 Advisory Non fatal Error Mask 12 RPLY_TMR_ST 0 R...

Page 1378: ...ue after reset Table 13 130 PCIE_CERR_MASK Register Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved 13 ADV_NFERR_MSK 1 Advisory Non fatal Error Mask 12 RPLY_TMR_MSK 0 Reply Ti...

Page 1379: ...neration Capable 4 0 FRST_ERR_PTR 0 First Error Pointer 13 4 9 8 HDR_LOG0 Register Figure 13 124 HDR_LOG0 Register 31 0 HDR_DW0 R 0 LEGEND R Read only n value after reset Table 13 132 HDR_LOG0 Registe...

Page 1380: ...ription 31 0 HDR_DW3 0 FFFF FFFFh Fourth DWORD of Header for a detected error 13 4 9 12 RC_ERR_CMD Register Figure 13 128 RC_ERR_CMD Register 31 8 Reserved R 0 7 3 2 1 0 Reserved FERR_RPT_EN NFERR_RPT...

Page 1381: ...0 Fatal Error Messages Received 5 NFERR 0 0h Non Fatal Error Messages Received 4 UNCOR_FATAL 0 First Uncorrectable Fatal 3 MULT_FNF 0 Multiple ERR_FATAL NONFATAL Received 2 ERR_FNF 0 ERR_FATAL NONFAT...

Page 1382: ...Bit Field Value Description 31 24 Reserved 0 Reserved 23 64BIT_EN 0 64 Bit address enabled Writable from internal bus interface 22 20 MULT_MSG_EN 0 7h Multiple Message Enabled Indicates that multiple...

Page 1383: ...R W Read Write n value after reset Table 13 142 MSI_UP32 Register Field Descriptions Bit Field Value Description 31 2 UP32_ADDR 0 3FFF FFFFh Upper 32 bit address 1 0 Reserved 0 Reserved 13 4 10 4 MSI...

Page 1384: ...7 PME_SUPP_N 0 1Fh PME Support Writable from internal bus interface 26 D2_SUPP_N 0 D2 Support Writable from internal bus interface 25 D1_SUPP_N 0 D1 Support Writable from internal bus interface 24 22...

Page 1385: ...red to zero 21 16 Reserved 0 Reserved 15 PME_STATUS 0 PME Status Indicates if a previously enabled PME event occurred or not 14 13 DATA_SCALE 0 3h Data Scale Not supported 12 9 DATA_SELECT 0 Fh Data s...

Page 1386: ..._LMT R W1S 40h LEGEND R W Read Write W1S Write 1 to set n value after reset Table 13 148 PL_ACKTIMER Register Field Descriptions Bit Field Value Description 31 16 RPLY_LIMT 0 FFFFh Replay Time Limit 1...

Page 1387: ...151 ACK_FREQ Register Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 ASPM_L1 0 Set to allow entering ASPM L1 even when link partner did not to L0s When cleared the ASPM L1 st...

Page 1388: ...ed 0 Reserved 21 16 LNK_MODE 0 3Fh Link Mode Enable 0 Reserved 1h 1 2h Reserved 3h 2 4h 6h Reserved 7h 4 8h Eh Reserved Fh 8 10h 1Eh Reserved 1Fh 16 20h 3Eh Reserved 3Fh 32 15 12 Reserved 0 Reserved 1...

Page 1389: ..._TIMER R W 0 R W 0 R W 0 R W 4h 15 14 13 11 10 8 7 4 3 0 REPLAY_TIMER Reserved SKP_COUNT NUM_TS2_SYMBOLS TS_COUNT R W 4h R 0 R W 3h R W Ah R W Ah LEGEND R W Read Write R Read only n value after reset...

Page 1390: ...Set to mask length match for received completion TLPs 25 F1_CPL_ATTR_TEST 0 Set to mask attribute match on received completion TLPs 24 F1_CPL_TC_TEST 0 Set to mask traffic class match on received comp...

Page 1391: ...S_LINK_CTRL TS_LANE_K237 TS_LINK_K237 RCVD_IDLE0 RCVD_IDLE1 R 0 R 0 R 0 R 0 R 0 23 8 PIPE_TXDATA R 0 7 6 5 4 0 PIPE_TXDATAK TXB_SKIP_TX LTSSM_STATE R 0 R 0 R 0 LEGEND R Read only n value after reset T...

Page 1392: ...RAINING 0 LTSSM performing link training 28 RCVR_REVRS_POL_EN 0 LTSSM testing for polarity reversal 27 TRAINING_RST_N 1 LTSSM negotiated link reset 26 23 Reserved 0 Reserved 22 PIPE_TXDETECTRX_LB 0 PI...

Page 1393: ...egister Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 DEEMPH 0 Set Deemphasis level for upstream ports 19 CFG_TX_CMPL 0 Configure TX Compliance Receive Bit 18 CFG_TX_SWIN...

Page 1394: ...1394 Peripheral Component Interconnect Express PCIe SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1395: ...eset Clock Management Overview 1404 14 3 Device Modules and Power Management Attributes List 1406 14 4 Clock Management 1409 14 5 Reset Management 1416 14 6 Power Management 1421 14 7 Registers 1424 1...

Page 1396: ...tching off and enabling of the clocks to the device modules The clocks are managed based on the requirement constraints of the associated modules The following sections identify the module clock chara...

Page 1397: ...protocol Clock management protocol between the PRCM and slave modules 14 1 2 1 Master Standby Protocol This protocol is used to indicate that a master module must initiate a transaction on the device...

Page 1398: ...acknowledge the request from the PRCM module and the PRCM module is then allowed to gate the clocks to the module A slave module is said to be in IDLE state when its clocks are gated by the PRCM modul...

Page 1399: ...igured behavior the PRCM module asserts the idle request to the module unconditionally that is immediately when the software requests Table 14 5 describes the configurable behavior of MODULEMODE Table...

Page 1400: ...ed clock manager within the PRCM module This allows the PRCM module to individually activate and gate each clock domain of the device Figure 14 2 Generic Clock Domain Figure 14 2 is an example of two...

Page 1401: ...led slave modules in the clock domain are provided All functional and interface clocks to the active master modules that is not in STANDBY in the clock domain are provided All enabled optional clocks...

Page 1402: ...hardware conditions are satisfied 2h SW_WKUP A software forced clock domain wake up transition is initiated 3h Reserved Reserved 14 1 4 Power Management The PRCM module manages the switching on and o...

Page 1403: ...s the current state of the logic area in the power domain LOGICSTATEST It can be OFF or ON PM_ Power domain _PWRSTST 5 4 Status Identifies the current state of the memory area in the power MEMSTATEST...

Page 1404: ...rol signals Clocks control signals Resets signals A set of power management protocol signals for each module to control and monitor standby idle and wake up modes CM and PRM Emulation signals 14 2 2 I...

Page 1405: ...ols required by PLLs will be generated by PLL controller PLL controllers will be configured controlled by chip level MMRs All the resets required by these MMRs PLL controllers will be generated by PRC...

Page 1406: ...al SIdleAck signal FCLKEN signal PRCM module handles all target modules wake up SWakeup signal 14 3 Device Modules and Power Management Attributes List 14 3 1 Active Power Domain Modules Attribute Tab...

Page 1407: ...SPINBOX ALWON_L3_SLOW_GCLK Slave TIMER1 ALWON_L3_SLOW_GCLK Slave TIMER2 ALWON_L3_SLOW_GCLK Slave TIMER3 ALWON_L3_SLOW_GCLK Slave TIMER4 ALWON_L3_SLOW_GCLK Slave TIMER5 ALWON_L3_SLOW_GCLK Slave TIMER6...

Page 1408: ...T_GCLK Slave EMIF4_1 L3_FAST_DEFAULT_GCLK Slave EMIF_FW L3_FAST_DEFAULT_GCLK Slave PCI PCI_GCLK Master Slave SATA L3_MED_DEFAULT_GCLK Master Slave USB USB_GCLK Master Slave 14 3 4 SGX Power Domain Mod...

Page 1409: ...Device delivers four clock signals to external devices Output clock SYSCLK_OUT can deliver clock outputs of each PLL CM_CLKOUT_CTRL Register controls the Clock selection and division ratio Table 14 17...

Page 1410: ...MHz SPI I2C SDIO and UART functional clock SYSCLK11 216 MHz Reserved SYSCLK13 165 MHz HDVPSS maximum SYSCLK14 27 MHz Reserved SYSCLK15 165 MHz HDVPSS maximum SYSCLK16 27 MHz Reserved SYSCLK17 54 MHz...

Page 1411: ...audio PLL 24 MHz clock for USB 27 MHz P PFD CP VCO N Preliminary www ti com Clock Management 14 4 4 Clock Generation 14 4 4 1 Main FAPLL Interface to PRCM Figure 14 6 shows the interface between main...

Page 1412: ...ry Clock Management www ti com 14 4 4 2 DDR FAPLL interface to PRCM Figure 14 7 shows the interface between DDR FAPLL and PRCM Figure 14 7 DDR FAPLL Interface to PRCM Table 14 20 DDR PLL Dividers Defa...

Page 1413: ...s the interface between video FAPLL and PRCM Figure 14 8 Video FAPLL Interface to PRCM Table 14 21 Video PLL Dividers Default Control Bit Filed Divider Supported Divide Ratios Value CM_SYSCLK11_CLKSEL...

Page 1414: ...clock Preliminary Clock Management www ti com 14 4 4 4 Audio FAPLL Interface to PRCM Figure 14 9 shows the interface between Audio FAPLL and PRCM Figure 14 9 Audio FAPLL Interface to PRCM Table 14 22...

Page 1415: ...SEL CLKSEL 0 1 2 1 CM_TIMER5_CLKSEL CLKSEL 0 1 2 1 CM_TIMER6_CLKSEL CLKSEL 0 1 2 1 Figure 14 11 shows McASP and McBSP clock select options For more information on Clocking and FAPLL refer to Chip Leve...

Page 1416: ...p power domain power up and E Fuse programming failures Warm reset types are not necessarily applied globally within each receiving entity A module may use a warm reset to reset a subset of its logic...

Page 1417: ..._PWRN_RST X X X X DSS_M3_RST1 X X X X X X X DSS_M3_RST2 X X X X X X X DSS_M3_RST3 X X X X X X X EMU_EARLY_PWRN_RST X X EMU_PWRN_RST X X X X EMU_RST X X X X X X X GEM_GRST X X X X X X X GEM_LRST X X X...

Page 1418: ...anism enforces the system requirement of a running 27 MHz clock 14 5 3 1 Power On Reset Sequence The following sequence describes the main chronological steps during the power on reset sequence of the...

Page 1419: ...ter release of the warm reset source until all the following conditions are met Device reset manager counter overflowed setup by the register PRM_RSTTIME RSTTIME2 Voltages are stable The external warm...

Page 1420: ...al the C674x subsystem starts the initialization sequence During the initialization sequence all the internal registers inside the C674x subsystem are properly reset and the reset for the DSP MMU and...

Page 1421: ...in the device See Figure 14 12 14 6 2 Power Domains Management PRCM contains a set of memory mapped PM type registers for those functional power domains These registers allow software to configure de...

Page 1422: ...0 Gigabit MAC USB 2 0 DSP subsystem Int ctrl 64x debug C674x DSP I Cache 32K D Cache 32K L2 cache 128K D D R I D I D S E R D E S S E R D E S U S B P H Y U S B P H Y TPTC0 TPTC1 TPTC2 TPTC3 EDMA TPCC 2...

Page 1423: ...errupt to the Cortex A8 All IPs that can generate wake up are always enabled 2 Software will request PRCM to put all Interface clock domains in the specific power domain in force wakeup by programming...

Page 1424: ...14 7 4 2 30Ch CM_SYSCLK4_CLKSEL Section 14 7 4 3 310h CM_SYSCLK5_CLKSEL Section 14 7 4 4 314h CM_SYSCLK6_CLKSEL Section 14 7 4 5 318h CM_SYSCLK7_CLKSEL Section 14 7 4 6 324h CM_SYSCLK10_CLKSEL Section...

Page 1425: ...ULT_FW_CLKCTRL Section 14 7 6 9 558h CM_DEFAULT_USB_CLKCTRL Section 14 7 6 10 560h CM_DEFAULT_SATA_CLKCTRL Section 14 7 6 11 574h CM_DEFAULT_CLKCTRL Section 14 7 6 12 578h CM_DEFAULT_PCI_CLKCTRL Secti...

Page 1426: ...Section 14 7 11 29 1584h CM_ALWON_TIMER_6_CLKCTRL Section 14 7 11 30 1588h CM_ALWON_TIMER_7_CLKCTRL Section 14 7 11 31 158Ch CM_ALWON_WDTIMER_CLKCTRL Section 14 7 11 32 1590h CM_ALWON_SPI_CLKCTRL Sec...

Page 1427: ...ed 1 Asserts a global COLD software reset The software must ensure the SDRAM is properly put in sef refresh mode before applying this reset 0 RST_GLOBAL_WARM_SW Global WARM software reset control This...

Page 1428: ...reset initiated by the emulation 0 No ICEPICK reset 1 IcePick reset has occurred 8 6 Reserved 0 Reserved 5 EXTERNAL_WARM_RST External warm reset event 0 No global warm reset 1 Global external warm re...

Page 1429: ...Reserved 0 Reserved 7 CLKOUT2EN This bit controls the external clock activity 0 SYS_CLKOUT2 is disabled 1 SYS_CLKOUT2 is enabled 6 Reserved 0 Reserved 5 3 CLKOUT2DIV This field controls the external c...

Page 1430: ...14 17 REVISION_PRM Register 31 8 7 0 Reserved REV R 0 R 10h LEGEND R W Read Write R Read only n value after reset Table 14 32 REVISION_PRM Register Field Descriptions Bit Field Value Description 31 8...

Page 1431: ...elect SYS_CLK divided by 7 7h Select SYS_CLK divided by 8 14 7 4 2 CM_SYSCLK2_CLKSEL Register The CM_SYSCLK2_CLKSEL register selects the divider value for SYSCLK2 It is shown and described in the figu...

Page 1432: ...erved CLKSEL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 14 35 CM_SYSCLK4_CLKSEL Register Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 CLKSEL Sel...

Page 1433: ...CLK divided by 1 1 Select SYS_CLK divided by 2 14 7 4 5 CM_SYSCLK6_CLKSEL Register The SCM_SYSCLK6_CLKSEL register selects the divider value for SYSCLK6 It is shown and described in the figure and tab...

Page 1434: ...LK10_CLKSEL Register The CM_SYSCLK10_CLKSEL register selects the divider value for SYSCLK10 It is shown and described in the figure and table below Figure 14 24 CM_SYSCLK10_CLKSEL Register 31 3 2 0 Re...

Page 1435: ...LK13_CLKSEL register selects the divider value for SYSCLK13 It is shown and described in the figure and table below Figure 14 26 CM_SYSCLK13_CLKSEL Register 31 3 2 0 Reserved CLKSEL R 0 R W 7h LEGEND...

Page 1436: ...Select SYS_CLK divided by 5 5h Select SYS_CLK divided by 6 6h Select SYS_CLK divided by 7 7h Select SYS_CLK divided by 8 14 7 4 11 CM_VPB3_CLKSEL Register The CM_VPB3_CLKSEL register selects the divid...

Page 1437: ...L Register The CM_VPD1_CLKSEL register selects the divider value for video PLL D1 divider It is shown and described in the figure and table below Figure 14 30 CM_VPD1_CLKSEL Register 31 2 1 0 Reserved...

Page 1438: ...CLK divided by 7 7h Select SYS_CLK divided by 8 14 7 4 15 CM_SYSCLK20_CLKSEL Register The CM_SYSCLK20_CLKSEL register selects the divider value for SYSCLK20 It is shown and described in the figure and...

Page 1439: ...divided by 6 6h Select SYS_CLK divided by 7 7h Select SYS_CLK divided by 8 14 7 4 17 CM_SYSCLK22_CLKSEL Register The CM_SYSCLK22_CLKSEL register selects the divider value for SYSCLK22 Figure 14 34 CM...

Page 1440: ...LK14 to be CLKIN 2h Select SYSCLK14 to be C1 divider output 3h Reserved 14 7 4 19 CM_SYSCLK16_CLKSEL Register The CM_SYSCLK16_CLKSEL register selects the Mux select line for SYSCLK16 clock It is shown...

Page 1441: ...KSEL Register The CM_AUDIOCLK_MCASP0_CLKSEL register selects the Mux select line for McASP0 audio clock It is shown and described in the figure and table below Figure 14 38 CM_AUDIOCLK_MCASP0_CLKSEL R...

Page 1442: ...t McASP1 audio clock to be SYSCLK22 3h Reserved 14 7 4 23 CM_AUDIOCLK_MCASP2_CLKSEL Register The CM_AUDIOCLK_MCASP2_CLKSEL register selects the Mux select line for McASP2 audio clock It is shown and d...

Page 1443: ...to be SYSCLK21 2h Select McASP2 audio clock to be SYSCLK22 3h Reserved 14 7 4 25 CM_TIMER1_CLKSEL Register The CM_TIMER1_CLKSEL register selects the Mux select line for TIMER1 clock It is shown and de...

Page 1444: ...X 2h Select TIMER clock to be CLKIN 3h Reserved 14 7 4 27 CM_TIMER3_CLKSEL Register The CM_TIMER3_CLKSEL register selects the Mux select line for TIMER3 clock It is shown and described in the figure a...

Page 1445: ...X 2h Select TIMER clock to be CLKIN 3h Reserved 14 7 4 29 CM_TIMER5_CLKSEL Register The CM_TIMER5_CLKSEL register selects the Mux select line for TIMER5 clock It is shown and described in the figure a...

Page 1446: ...ed 14 7 4 31 CM_SYSCLK23_CLKSEL Register The CM_SYSCLK23_CLKSEL register selects the divider value for SYSCLK23 It is shown and described in the figure and table below Figure 14 48 CM_SYSCLK23_CLKSEL...

Page 1447: ..._SYSCLK24_CLKSEL Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 CLKSEL Selects the divider value warm reset insensitive 0 Select SYS_CLK divided by 1 1h Select SY...

Page 1448: ...erved 10 CLKACTIVITY_GEM_TRCCLK This field indicates the state of the GEM_TRCCLK clock in the domain 0 Corresponding clock is gated 1 Corresponding clock is active 9 CLKACTIVITY_GEM_VBUSPCLK This fiel...

Page 1449: ...the state of the L3_EN_GCLK clock in the domain 0 Corresponding clock is gated 1 Corresponding clock is active 14 CLKACTIVITY_PRC_GCLK This field indicates the state of the PRC_GCLK clock in the domai...

Page 1450: ...g clock is gated 1 Corresponding clock is active 7 2 Reserved 0 Reserved 1 0 CLKTRCTRL Controls the clock state transition of the HD DSS clock domain 0 Reserved 1h SW_SLEEP Start a software forced sle...

Page 1451: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1452: ...including OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled an...

Page 1453: ...ITY_L3_MED_GCLK Reserved CLKTRCTRL R 0 R 0 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 14 69 CM_DEFAULT_L3_MED_CLKSTCTRL Register Field Descriptions Bit Field Value Descripti...

Page 1454: ...ster Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 CLKACTIVITY_DDR_GCLK This field indicates the state of the DDR_GCLK clock in the domain 0 Corresponding clock is gated 1...

Page 1455: ...r reset Table 14 71 CM_DEFAULT_PCI_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_PCI_GCLK This field indicates the state of the PCI_GCLK cloc...

Page 1456: ...14 72 CM_DEFAULT_L3_SLOW_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_USB_GCLK This field indicates the state of the L3_SLOW_GCLK clock in t...

Page 1457: ...Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 CLKACTIVITY_GCLKIN200TR This field indicates the state of the CLKIN200TR clock in the domain 0 Corresponding clock is gated 1 Corre...

Page 1458: ...wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0...

Page 1459: ...wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0...

Page 1460: ...r sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMO...

Page 1461: ...or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEM...

Page 1462: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1463: ...including OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and...

Page 1464: ...P 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be a...

Page 1465: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1466: ...after reset Table 14 82 CM_SGX_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_SGX_GCLK This field indicates the state of the SGX_GCLK clock i...

Page 1467: ...ransition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Res...

Page 1468: ...W Read Write R Read only n value after reset Table 14 84 PM_ACTIVE_PWRSTCTRL Register Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reserved 17 16 ACTIVE_MEM_ONSTATE Active domain m...

Page 1469: ...ead only n value after reset Table 14 85 PM_ACTIVE_PWRSTST Register Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 INTRANSITION Domain transition status 0 No on going tran...

Page 1470: ...reset 1 Reset is asserted for the active domain C674x DSP warm reset 14 7 8 4 RM_ACTIVE_RSTST Register The RM_ACTIVE_RSTST register logs the different reset sources of the ACTIVE domain Each bit is s...

Page 1471: ...LEGEND R W Read Write R Read only n value after reset Table 14 88 PM_DEFAULT_PWRSTCTRL Register Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reserved 17 16 DEFAULT_MEM_ONSTATE Defau...

Page 1472: ...Read only n value after reset Table 14 89 PM_DEFAULT_PWRSTST Register Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 INTRANSITION Domain transition status 0 No on going tr...

Page 1473: ...al reset control 0 Reset is cleared for PCIe 1 Reset is asserted for PCIe 6 5 Reserved 3h Reserved Always write the default value for future device compatibility 4 RST3 Logic and MMU reset control 0 R...

Page 1474: ...Value Description 31 8 Reserved 0 Reserved 7 PCI_LRST PCI local software reset 0 No software reset occurred 1 PCI has been reset upon software reset 6 5 Reserved 0 Reserved Always write the default va...

Page 1475: ...3h Memory bank is on when the domain is ON 15 2 Reserved 0 Reserved 1 0 POWERSTATE Power state control 0 OFF State warm reset insensitive 1h Reserved 2h Reserved 3h ON State warm reset insensitive 14...

Page 1476: ...te status 0 OFF State 1h Reserved 2h Reserved 3h ON State 1 0 POWERSTATEST Current Power State Status 0 OFF State 1h Reserved 2h Reserved 3h ON State 14 7 10 4 RM_SGX_RSTST Register This register logs...

Page 1477: ...VITY_MCASP1_AUX_ CLKACTIVITY_MCASP0_AUX_ CLKACTIVITY_L3_SLOW_GCLK GCLK GCLK GCLK R 0 R 0 R 0 R 0 7 2 1 0 Reserved CLKTRCTRL R 0 R W 2h LEGEND R W Read Write R Read only n value after reset Table 14 96...

Page 1478: ...ate of the GPIO_GDBCLK clock in the domain 0 Corresponding clock is gated 1 Corresponding clock is active 14 CLKACTIVITY_GPIO_0_GDBCLK This field indicates the state of the GPIO_GDBCLK clock in the do...

Page 1479: ...gated 1 Corresponding clock is active 7 2 Reserved 0 Reserved 1 0 CLKTRCTRL Controls the clock state transition of the L3_SLOW clock domain in Always ON power domain 0 Reserved 1h SW_SLEEP Start a sof...

Page 1480: ...Field Value Description 31 10 Reserved 0 Reserved 9 CLKACTIVITY_RFT_GCLK This field indicates the state of the CPGMAC_RFT_GCLK clock in the domain 0 Corresponding clock is gated 1 Corresponding clock...

Page 1481: ...ter enables the domain power state transition It controls the software supervised clock domain state transition between ON ACTIVE and ON INACTIVE states It also hold one status bit per clock input of...

Page 1482: ...Table 14 100 CM_MMUCFG_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_MMU_CFG_GCLK This field indicates the state of the MMU_CFG_GCLK clock i...

Page 1483: ...14 101 CM_ALWON_OCMC_0_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_OCMC_0_GCLK This field indicates the state of the OCMC_0_GCLK clock in t...

Page 1484: ...4 102 CM_ALWON_OCMC_1_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_OCMC_1_GCLK This field indicates the state of the OCMC_1_GCLK clock in th...

Page 1485: ...4 103 CM_ALWON_MPU_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_MPU_GCLK This field indicates the state of the MPU_GCLK clock in the domain...

Page 1486: ...e state of the L3_F_EN_GCLK clock in the domain 0 Corresponding clock is gated 1 Corresponding clock is active 10 CLKACTIVITY_L3_S_GCLK This field indicates the state of the L3_S_GCLK clock in the dom...

Page 1487: ...value after reset Table 14 105 CM_ALWON_SYSCLK5_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_SYSCLK5_GCLK This field indicates the state of...

Page 1488: ...value after reset Table 14 106 CM_ALWON_SYSCLK6_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_SYSCLK6_GCLK This field indicates the state of...

Page 1489: ...R Read only n value after reset Table 14 107 CM_ALWON_RTC_CLKSTCTRL Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLKACTIVITY_RTC_GCLK This field indicates the sta...

Page 1490: ...Description 31 10 Reserved 0 Reserved 9 CLKACTIVITY_FAST_GCLK This field indicates the state of the L3 Fast clock for TPTC and TPCC in the domain 0 Corresponding clock is gated 1 Corresponding clock...

Page 1491: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1492: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1493: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1494: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1495: ...eup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MOD...

Page 1496: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1497: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1498: ...only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 9 Reserved 0 Reserved 8 OPTFCLKEN_DBCLK Optional functional clock control 0 Optional...

Page 1499: ...e only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 9 Reserved 0 Reserved 8 OPTFCLKEN_DBCLK Optional functional clock control 0 Optional...

Page 1500: ...or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEM...

Page 1501: ...or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEM...

Page 1502: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1503: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1504: ...p or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE Con...

Page 1505: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1506: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1507: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1508: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1509: ...eup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MOD...

Page 1510: ...eep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE C...

Page 1511: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1512: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1513: ...keup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MO...

Page 1514: ...eup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MOD...

Page 1515: ...sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE...

Page 1516: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1517: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1518: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1519: ...sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE...

Page 1520: ...unctional including OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is di...

Page 1521: ...unctional including OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is di...

Page 1522: ...OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot b...

Page 1523: ...or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE Cont...

Page 1524: ...leep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE...

Page 1525: ...leep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE...

Page 1526: ...ep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE Co...

Page 1527: ...sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODULEMODE...

Page 1528: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1529: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1530: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1531: ...cluding OCP 1h Module is performing transition wakeup or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and c...

Page 1532: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1533: ...p or sleep or sleep abortion 2h Module is in Idle mode only OCP part It is functional if using separate functional clock 3h Module is disabled and cannot be accessed 15 2 Reserved 0 Reserved 1 0 MODUL...

Page 1534: ...1534 Power Reset and Clock Management PRCM Module SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1535: ...C This chapter provides a functional presentation of real time clock RTC Topic Page 15 1 Introduction 1536 15 2 Architecture 1537 15 3 Registers 1544 1535 SPRUGX9 15 April 2011 Real Time Clock RTC Sub...

Page 1536: ...wake the rest of chip up from a power down state Alarms are available to interrupt the CPU at a particular time or at periodic time intervals such as once per minute or once per day In addition the RT...

Page 1537: ...be used instead of a crystal In such a case the clock source is connected to RTC_XI and RTC_XO is left unconnected If the RTC is not used the RTC_XI pin should be held low and RTC_XO should be left u...

Page 1538: ...y occurs when the elapsed hour minute or second corresponds to the start of a new day Table 15 2 Interrupt Trigger Events One day has passed One hour has passed One minute has passed One second has pa...

Page 1539: ...gisters which share the names above also share the same BCD formatting SECOND Second Count 00 59 MINUTE Minute Count 00 59 HOUR Hour Count 12HR 01 12 24HR 00 23 DAY Day of the Month Count 01 31 WEEK D...

Page 1540: ...NUTE SECOND registers to the nearest minute with zero seconds This feature is enabled by setting the ROUND_30S bit in the control register CTRL the RTC automatically rounds the time values to the near...

Page 1541: ...the STATUS_REG bit 1 needs to be checked to verify the RTC has in fact stopped Once this is confirmed the TC values can be updated After the values have been updated the RTC can be re started by rese...

Page 1542: ...ate the drift compensation versus one hour period and load the compensation registers with the drift compensation value Auto compensation is enabled by AUTO_COMP_EN bit in the RTC_CTRL register If the...

Page 1543: ...e the registers section 15 2 6 Power Management The RTC supports the power idle protocol It has two SWakeup ports one for the alarm event and one for a timer event When the RTC is in IDLE mode the OCP...

Page 1544: ...G Alarm Days Register 30h ALARM_MONTHS_REG Alarm Months Register 34h ALARM_YEARS_REG Alarm Years Register 40h RTC_CTRL_REG Control Register 44h RTC_STATUS_REG Status Register 48h RTC_INTERRUPTS_REG In...

Page 1545: ...nge is 0 to 5 3 0 SEC0 0 9h 1st digit of seconds Range is 0 to 9 15 3 2 Minutes Register MINUTES_REG The MINUTES_REG is used to program the minutes value of the current time Minutes are stored as BCD...

Page 1546: ...0 Reserved 5 4 HOUR1 0 2h 2nd digit of hours Range is 0 to 2 3 0 HOUR0 0 9h 1st digit of hours Range is 0 to 9 15 3 4 Days of the Month Register DAYS_REG The DAYS_REG is used to program the day of the...

Page 1547: ...NTH0 0 9h 1st digit of months Range is 0 to 9 15 3 6 Year Register YEARS_REG The YEARS_REG is used to program the year value of the current date The year value is represented by only the last 2 digits...

Page 1548: ...it of days in a week Range from 0 Sunday to 6 Saturday 15 3 8 Alarm Second Register ALARM_SECONDS_REG The ALARM_SECONDS_REG is used to program the second value for the alarm interrupt Seconds are stor...

Page 1549: ...is 0 to 9 15 3 10 Alarm Hour Register ALARM_HOURS_REG The ALARM_HOURS_REG is used to program the hour value for the alarm interrupt Hours are stored as BCD format In BCD format the decimal numbers 0...

Page 1550: ...to 3 3 0 ALARM_DAY0 0 9h 1st digit for days Range from 0 to 9 15 3 12 Alarm Month Register ALARM_MONTHS_REG The ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt...

Page 1551: ...15 18 Alarm Year Register ALARM_YEARS_REG 31 16 Reserved R 0 15 8 7 4 3 0 Reserved ALARM_YEAR1 ALARM_YEAR0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 17 Alarm Year...

Page 1552: ...1 RTC disable no 32 kHz clock 5 SET_32_COUNTER Set the 32 kHz counter with the value stored in the compensation registers when the SET_32_COUNTER bit is set 0 No action 1 Set the 32Khz counter with co...

Page 1553: ...alue is positive compensation occurs after the second change event COMP_REG cycles are removed from the next second If the COMP_REG value is negative compensation occurs before the second change event...

Page 1554: ...is bit will indicate the status of the alarm interrupt Writing a 1 to the bit clears the interrupt 1D_EVENT1 This bit will indicate if a day event has occurred An interrupt will be generated to the pr...

Page 1555: ...upt when the alarm value is reached TC ALARM registers by the TC registers 2 IT_TIMER Enable periodic interrupt 0 Interrupt disabled 1 Interrupt enabled 1 0 EVERY 0 3h Interrupt period 0 Every second...

Page 1556: ...0 LEGEND R W Read Write R Read only n value after reset Table 15 21 Compensation LSB Register COMP_LSB_REG Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RTC_COMP_LSB 0 F...

Page 1557: ...ved RTC_COMP_MSB R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 22 Compensation MSB Register COMP_MSB_REG Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reser...

Page 1558: ...SPROG 0 Fh Value of the oscillator resistance NOTE SW_RESET bit is set to 1 to reset the RTC module This bit is self clearing and is always read as 0 CPU must care of interrupt handling before RTC is...

Page 1559: ...n to KICK0R Figure 15 26 Kick0 Register KICK0R 31 0 KICK0 W 0 LEGEND W Write only n value after reset Table 15 25 Kick0 Register KICK0R Field Descriptions Bit Field Value Description 31 0 KICK0 0 Kick...

Page 1560: ...C_SYSCONFIG Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 IDLEMODE 0 3h Configuration of the local target state management mode By definition target can handle read write...

Page 1561: ...Read only n value after reset Table 15 29 Wakeup Enable Register RTC_IRQWAKEEN Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ALARM_WAKEEN Wakeup generation for event Alarm...

Page 1562: ...1562 Real Time Clock RTC SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1563: ...hapter describes the Serial ATA Controller SATA in the device Topic Page 16 1 Introduction 1564 16 2 Architecture 1568 16 3 Use Cases 1574 16 4 Registers 1592 1563 SPRUGX9 15 April 2011 Serial ATA SAT...

Page 1564: ...roller that is supported by the device supports AHCI mode of operation only That is the AHCI controller supported has no support for Legacy mode of operation AHCI is a PCI class device that acts as a...

Page 1565: ...entries 32 bit addressing Supports port multiplier with command based switching Activity LED support one for each Port 16 1 3 Features Not Supported Features not supported in this SATA controller are...

Page 1566: ...ram The SATASS is a fully contained Serial ATA host with built in DMA It uses the AHCI standard for communication with a SATA device It has no support for the Legacy mode of operation Figure 16 1 show...

Page 1567: ...the direction of the transmission of FIS which is from HBA host to device HBA HBA is an acronym for host bus adapter It is the SATA controller that implements the AHCI specification to communicate be...

Page 1568: ...low jitter external differential clock is required as a source clock input to the PHY and the frequency of the input clock should be between 60MHz and 375 MHz depending upon the supported multiplier...

Page 1569: ...2 3 DMA Each HBA ports contain two DMA engines One of the DMA engine is used to fetch command from the command list The other DMA is used to move FISes in and out of system memory The DMA used to move...

Page 1570: ...ledgment and status Data width conversion Data scrambling descrambling Primitive transmission Primitive detection and dropping Power management 16 2 7 PHY The SATASS includes an integrated TI SERDES m...

Page 1571: ...device No dedicated signals for controlling power and device detection are not bonded out and usage of GPIO pins can be used to supplement this task However the controller supports the capability to...

Page 1572: ...ster PI AHCI version register VS global parameter 1 register GPARAM1R global parameter 2 register GPARAM2R and the port parameter register PPARAMR to obtain information about the subsystem s capabilit...

Page 1573: ...equency of 250 MHz the 1ms cycle count should be programmed with a value of 250 000 i e 250 MHz 1000 250000d and CCC_CTL TV is programmed with a non Zero value 15 in this case When CCC_CTL EN is set t...

Page 1574: ...res properly aligned system memory resources initialization as well as performing basic DMA Read Write transfer using a couple of the Command Slots Section 16 3 1 contains examples in relations to Sys...

Page 1575: ...is 32 define WRITE_CMD_SLOT 0 Value used here should be LISTLENGTH 1 define READ_CMD_SLOT 1 Value used here should be LISTLENGTH 1 WARNING PRDLENGTH can not be greater than 8 for this program See Not...

Page 1576: ...Uint32 CmdTableAddLow 25 bits 31 7 Uint32 CmdTableAddLow bits 31 7 CmdListHeaderW2 typedef struct Uint32 CmdTableAddHigh bits 31 0 CmdListHeaderW3 typedef struct CmdListHeaderW0 DW0 CmdListHeaderW1 DW...

Page 1577: ...truct Uint32 DbaHigh bits 31 0 DbaAddressHigh typedef struct Uint32 DW2Reserved bits 31 0 PrdtRsv typedef struct Uint32 DataBC 22 bits 21 0 DataByteCnt typedef struct DbaAddressLow DW0 DbaAddressHigh...

Page 1578: ...Uint32 DW6Rsv DMASetupFis DMA Setup FIS end PIO Setup FIS typedef struct Uint32 B0FisType 8 bits 7 0 Uint32 BYTE1 8 bits 15 8 Uint32 B2Status 8 bits 23 16 Uint32 B3Errror 8 bits 31 24 PioSetupDW0 type...

Page 1579: ...int32 B1SecCntExp 8 bits 15 8 Uint32 HW1Rsv 16 bits 31 16 D2HRegDW3 typedef struct Uint32 W0Rsv bits 31 0 D2HRegDW4 typedef struct D2HRegDW0 DW0 D2HRegDW1 DW1 D2HRegDW2 DW2 D2HRegDW3 DW3 D2HRegDW4 DW4...

Page 1580: ...isDw1Dev Uint8 cfisDw2SecNumLbaLowExp Uint8 cfisDw2CylLowLbaMidExp Uint8 cfisDw2CylHighLbahighExp Uint8 cfisDw2FeatureExp Uint8 cfisDw3SecCnt Uint8 cfisDw3SecCntExp Uint8 cfisDw3Ctrl cmdFis typedef st...

Page 1581: ...0 0 void clearCmdTables void Uint16 cmdSlot for cmdSlot 0 cmdSlot LISTLENGTH cmdSlot Clear Command FIS and ATAPI Command Spaces for Command Header X LISTLENGTH X 0 initMemory Uint32 CmdTable cmdSlot...

Page 1582: ...that it is not initialized Dev28bitLbaAddress 0xFFFFFFFF S W needs to initialize this variable prior to calling _INT_DRIVEN_TEST_ is defined within the Project File ifdef _INT_DRIVEN_TEST_ intHandling...

Page 1583: ...rts Staggered Spinup capability and P0CMD SUD is cleared to Zero when HBA Reset takes place Software needs to invoke this if needed Most likely user want to ensure HBA comes up in its default operatio...

Page 1584: ...ed unsigned char iSpeed sataRegs P0SCTL iSpeed AHCI_PxSCTL_PxSSTS_SPD_SHIFT waitForXms 5 This might not be necessary wait a bit char setupCfisEntriesForDataRdWr CmdListHeader CmdListNum dataXferDir re...

Page 1585: ...Wr and Cleared for Control Wr myCmdFis cfisByte1 CMDFIS_BYTE1_C_IS_CTRL_UPDATE Bit7 of Byte1 is Cleared for Command Control Wr if readOrWrite DATA_DIR_WR if xferType DMA_PROTOCOL myCmdFis cfisCmd ATA...

Page 1586: ...umLbaLowExp 0x0 CmdSlotNum cfis DW2 B1LbaMidExp myCmdFis cfisDw2CylLowLbaMidExp 0x0 CmdSlotNum cfis DW2 B2LbaHighExp myCmdFis cfisDw2CylHighLbahighExp 0x0 CmdSlotNum cfis DW2 B3FeatureExp myCmdFis cfi...

Page 1587: ...Configuration values Need to configure this prior to calling sata_init_and_spin_up swCtrlFeatures capSMPS 1 Input Pin exist for external activity detection presence swCtrlFeatures capSSS 1 Always set...

Page 1588: ...pecificField int type GLOBALint or PORTint intState DISABLE or ENABLE enableDisableInt GLOBALint ENABLE 0 enableDisableInt int type intState specificField int type GLOBALint or PORTint intState DISABL...

Page 1589: ...aBuff cmdSlot2Use sata_input_prdLength DATABUFFERLEN 4 0x12345678 0x01010101 Configure Device 28 bit LBA Address Start Address for Rd Wr Transfer Dev28bitLbaAddress sata_input_startAddress 28 Bit LBA...

Page 1590: ...Preliminary Use Cases www ti com 1590 Serial ATA SATA Controller SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1591: ...sata_input_prdLength DATABUFFERLEN 4 0xDEADBEEF 0x00000000 Configure Device 28 bit LBA Address Start Address for Rd Wr Transfer Dev28bitLbaAddress sata_input_startAddress 28 Bit LBA Address setupCfis...

Page 1592: ...at pertains to the specific port reside within this space There are as many register banks as there are ports for this device two banks of registers are available Table 16 3 lists the registers of the...

Page 1593: ...0 188h P1FB Port 1 FIS Base Address Register Section 16 4 21 190h P1IS Port 1 Interrupt Status Register Section 16 4 22 194h P1IE Port 1 Interrupt Enable Register Section 16 4 23 198h P1CMD Port 1 Com...

Page 1594: ...table once after power up Set this bit during Firmware Initialization prior to attempting to spin up device P0CMD SUD 26 SALP 1 Supports Aggressive Link Power Management SATASS supports auto generatin...

Page 1595: ...CI mode as indicated by the SAM bit in the HBA capabilities register CAP 1 30 2 Reserved 0 Reserved 1 IE Interrupt Enable This global bit enables interrupts from the SATASS This field is reset on Glob...

Page 1596: ...ld Value Description 31 2 Reserved 0 Reserved 1 0 IPS n 0 1 Interrupt Pending Status IPS 0 is for Port 0 and IPS 1 is for Port 1 If a bit n is set to 1 If set the corresponding Port has an interrupt p...

Page 1597: ...plemented Register PI Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 PI n 0 1 Ports Implemented This register is bit significant If a bit n is set to 1 the corresponding P...

Page 1598: ...Completions This bit field specifies the number of command completions that are necessary to cause a CCC interrupt Software loads this value prior to enabling CCC This bit field is Read Write R W when...

Page 1599: ...R 0 R W 0 LEGEND R W Read Write n value after reset Table 16 10 Command Completion Coalescing Ports Register CCC_PORTS Field Description Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 PRT Th...

Page 1600: ...ency test pattern LFTP 7Fh Simultaneous switching outputs pattern SSOP 80h 8Ah Reserved 8Bh Lone Bit pattern LBP 8Ch AAh Reserved ABh Low frequency spectral component pattern LFSCP ACh B4h Reserved B5...

Page 1601: ...PHY Link NOCOMM state BIST Activate FIS is not sent to the device in this mode 15 11 Reserved 0 Reserved 10 8 LLC 0 7h Link Layer Control This bit field controls the Port Link Layer functions scramble...

Page 1602: ...ng SATA compliant patterns for far end retimed far end analog near end analog initiator modes or non compliant patterns for transmit only responder mode when initiated by software writing to the BISTC...

Page 1603: ...modes It is not meaningful in responder mode It is updated each time a new BIST FIS is received It is reset by Global reset Port reset COMRESET or by setting the BISTCR CNTCLR bit The BISTSR register...

Page 1604: ...reezes if it exceeds FFFF F000h 16 4 13 BIST DWORD Error Count Register TIMER1MS The BIST DWORD error count register TIMER1MS is used to generate 1ms tick for the command completion coalescing CCC log...

Page 1605: ...s an Rx Data Buffer 29 28 PHY_DATA 0 PHY Data Width Indicates width 0 8 bits 27 PHY_RST 0 PHY Reset Mode Indicates that the PHY reset output is active low 26 21 PHY_CTRL 1Ah PHY Control Width Indicate...

Page 1606: ...ld Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 DEV_CP 0 Cold Presence Detect CPD is supported in SATASS 13 DEV_MP 0 Mechanical Presence Switch MP is supported in SATASS 12 EN...

Page 1607: ...et Table 16 19 Port Parameter Register PPARAMR Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 TX_MEM_M 0 Tx FIFO Memory Read Port Type Indicates that the Tx FIFO memory is...

Page 1608: ...e GHC register IE bit BISTAFR register NCP and PD bits become read write BISTCR register LLC ERREN FLIP PV PATTERN BISTFCTR BISTSR BISTDECR registers become read write P CLB 0 or 1 CLBU P FB 0 or 1 FB...

Page 1609: ...Description Bit Field Value Description 31 0 VERSION 3134 302Ah 32 bit version of SATASS 16 4 19 ID Register IDR The ID register IDR contains the 32 bit SATASS ID The IDR register is shown in Figure 1...

Page 1610: ...This address must be 1Kbyte aligned as indicated by bits 9 0 being read only 9 0 Reserved 0 Reserved 16 4 21 Port FIS Base Address Register P FB 0 or 1 The port FIS base address register P FB contain...

Page 1611: ...ERR ERR_C Unknown FIS is received with good CRC but the length exceeds 64 bytes PRD table byte count is zero Port DMA transitions to a fatal state until software clears P0CMD ST bit or resets the inte...

Page 1612: ...When set to 1 indicates that an unknown FIS was received and has been copied into system memory This bit is cleared to 0 by software clearing the P0SERR DIAG_F bit to 0 Note The UFS bit does not direc...

Page 1613: ...1 GHC IE 1 and P0IS HBDS 1 the intrq output is asserted 27 IFE 0 1 Interface Fatal Error Enable When set to 1 GHC IE 1 and P0IS IFS 1 the intrq output is asserted 26 INFE 0 1 Interface Non fatal Erro...

Page 1614: ...reads this value it indicates the Port is ready to accept a new interface control command although the transition to the previously selected state may not yet have occurred 1h Active Causes the Port...

Page 1615: ...ns from 0 to 1 the highest priority slot to issue from next is command slot 0 After the first command has been issued the highest priority slot to issue from next is P0CMD CCS 1 For example after the...

Page 1616: ...and list Whenever this bit is changed from a 0 to a 1 the Port starts processing the command list at entry 0 Whenever this bit is changed from a 1 to a 0 the P0CI register is cleared by the Port upon...

Page 1617: ...Reserved 3h DRQ Indicates a data transfer is requested 4h 6h Reserved 7h BSY Indicates the interface is busy 8h FFh Reserved 16 4 26 Port Signature Register P SIG 0 or 1 The port signature register P...

Page 1618: ...te 0 Device is not present or communication is not established 1h Interface in active state 2h Interface in Partial power management state 3h 5h Reserved 6h Interface in Slumber power management state...

Page 1619: ...vice to enter that state is rejected via PMNAKp 0 No interface power management state restrictions 1h Transitions to the Partial state are disabled 2h Transitions to the Slumber state are disabled 3h...

Page 1620: ...ype field that was not recognized known and the length was less than or equal to 64 bytes Note If the Unknown FIS length exceeds 64 bytes the DIAG_F bit is not set and the DIAG_T bit is set instead 24...

Page 1621: ...e or problems with the interface but not after transition from active to Partial or Slumber power management state 8 ERR_T 0 1 Non recovered Transient Data Integrity Error This bit is set if any of th...

Page 1622: ...ted successfully Software should only write to this bit field when P0CMD ST bit is set to 1 This bit field is cleared when P0CMD ST is written from a 1 to a 0 by software This bit field is not cleared...

Page 1623: ...Field Value Description 31 2 Reserved 0 Reserved 1 0 PMN n 0 1 PM Notify Indicates whether a particular device with the corresponding PM Port number issued a Set Device Bits FIS to the SATASS Port wit...

Page 1624: ...DWORDs 5h Limit OCP Burst size to 16 DWORDs 6h Limit OCP Burst size to 32 DWORDs 7h Limit OCP Burst size to 64 DWORDs 9h Fh Limit OCP Burst size to 256 DWORDS Note The maximum sized burst that will b...

Page 1625: ...be set instead 0 1 DWORD 1h 2 DWORDs 2h 4 DWORDs 3h 8 DWORDs 4h 16 DWORDS 5h 32 DWORDs 6h 64 DWORDs 7h Fh Reserved 3 0 TXTS 0 Fh Transmit Transaction Size TX_TRANSACTION_SIZE This field defines the D...

Page 1626: ...RXENOC RXEQ R W 0 R W 0 R W 0 R W 0 R W 0 15 13 12 11 10 9 8 RXCDR RXLOS LOOPBACK RXINVPAIR CLKBYP R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 1 0 CLKBYP LB MPY ENPLL R W 0 R W 0 R W 0 R W 0 LEGEND R W Read...

Page 1627: ...1000 tbd 22 TXCM Transmitter Common Mode 0 Normal Common Mode 1 Raised common mode 21 TXINVPAIR 0 Transmitter Invert Polarity Inverts the polarity of TXP and TXN 20 RXENOC Receiver Offset Compensation...

Page 1628: ...on Note This must be enabled by software before initialization is started on the device Note Refer to PHY CFGR2 Register for what value is actually programmed into the SERDES In most cases only the de...

Page 1629: ...n MPY 4 b0001 5x Note This field should only be written before or at the same time while enabling the ENPLL field You should not change MPY field after the PLL is enabled Note This field applies to Po...

Page 1630: ...d described in Table 16 38 Figure 16 36 Port PHY Status Register P PHYSR 31 16 Reserved R 0 15 1 0 Reserved SIGDET LOCK R 0 R 0 R 0 LEGEND R Read only n value after reset Table 16 38 Port PHY Status R...

Page 1631: ...ink is not in a low power state it will ruin the link and cause undetermined behavior A port reset or full SATASS reset may be required to recover 0 Normal 1 Override 16 OVERRIDE0 Override for Clock S...

Page 1632: ...to 0x1 ON and in most cases will never have to be changed However if a system is experiencing a large amount of incorrect commas detected software may use this register to disable comma alignment aft...

Page 1633: ...s This chapter describes the operation of the software programmable timer Topic Page 17 1 Introduction 1634 17 2 Architecture 1635 17 3 Registers 1644 1633 SPRUGX9 15 April 2011 Timers Submit Document...

Page 1634: ...CP clock cycles In order to improve module access latency and under restricted conditions on clocks ratios write posted mode can be used by setting the POSTED bit of the System Control Register TSCR U...

Page 1635: ...Control Register TCLR ST bit The Timer Counter Register TCRR can be loaded when stopped or on the fly while counting TCRR can be loaded directly by a TCRR Write access with the new timer value TCRR c...

Page 1636: ...nored no update on TCAR1 and no interrupt triggering until the detection logic is reset or the interrupt status register is cleared on TCAR s position writing a 1 in it If TCLR s CAPT_MODE field is 1...

Page 1637: ...tcapt_resync capt_pulse int_serve clear_trig FSM State tcar1_enable TCRR TCAR1 TCAR2 OCKED LOCKED1 NEW_VALUE Capture ignored Capture ignored NEW_VALUE UN LOCKED LOCKED2 LOCKED1 UN LO LOCKED2 tcar2_ena...

Page 1638: ...n PORTIMERPWM output The PORTIMERPWM output pin can be configured to toggle on specified event TCLR TRG bits determines on which register value the PORTIMERPWM pin toggles Either overflow or match can...

Page 1639: ...timer_pwm TRG 01 PT 0 timer_pwm TRG 10 PT 0 timer_pwm TRG 10 PT 1 timer_pwm TRG 01 PT 1 Set up mode sequence First match event ignored Preliminary www ti com Architecture Figure 17 5 Timing Diagram o...

Page 1640: ...2 PTV 1 As an example if we consider a timer clock input of 32 kHz with a PRE field equal to 0 the timer output period is Table 17 4 Value and Corresponding Interrupt Period TLDR Interrupt period 000...

Page 1641: ...3 OCP Error Generation The timer module responds with error indication in the following cases Error on write transactions Assert the PORSRESP ERR signal in the same cycle as PORSCMDACCEPTED Use the E...

Page 1642: ...internal register The write transaction is immediately acknowledged on the OCP interface although the effective write operation will occur later due to a resynchronisation in the timer clock domain T...

Page 1643: ...is mode uses a posted read scheme for reading any internal register The read transaction is immediately acknowledged on the OCP interface and the value to be read has been previously resynchronised Th...

Page 1644: ...egister 28h IRQSTATUS Timer IRQSTATUS Register 2Ch IRQSTATUS_SET Timer IRQENABLE Set Register 30h IRQSTATUS_CLR Timer IRQENABLE Clear Register 34h IRQWAKEEN Timer IRQ Wakeup Enable Register 38h TCLR T...

Page 1645: ...tained by IP specification owner X changes ONLY when 1 There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field or Class Type in old PID format will rem...

Page 1646: ...Backup mode for debug only 2h Smart idle mode local target s idle state eventually follows acknowledges the system s idle requests depending on the IP module s internal requirements IP module shall no...

Page 1647: ...EOI Register IRQ_EOI 31 1 4 0 Reserved LINE_NUMBER R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 9 Timer IRQ EOI Register IRQ_EOI Field Descriptions Bit Field Value Descript...

Page 1648: ...ite R Read only n value after reset Table 17 10 Timer IRQSTATUS Raw Register IRQSTATUS_RAW Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 TCAR_IT_FLAG IRQ status for Capture...

Page 1649: ...W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 11 Timer IRQSTATUS Register IRQSTATUS Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 TCAR_IT_...

Page 1650: ...ter reset Table 17 12 Timer IRQENABLE Set Register IRQENABLE_SET Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 TCAR_EN_FLAG IRQ enable for Compare R0 IRQ event is disabled...

Page 1651: ...after reset Table 17 13 Timer IRQENABLE Clear Register IRQENABLE_CLR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 TCAR_EN_FLAG IRQ enable for Compare R0 IRQ event is disab...

Page 1652: ...eration for Overflow 0 Wakeup disabled 1 Wakeup enabled 0 MAT_WUP_ENA Wakeup generation for Match 0 Wakeup disabled 1 Wakeup enabled 17 3 9 Timer Control Register TCLR NOTE When the TCM field passed f...

Page 1653: ...2h Capture on high to low transition 3h Capture on both edge transition 7 SCPWM This bit should be set or clear while the timer is stopped or the trigger is off 0 Clear the PORTIMERPWM output pin and...

Page 1654: ...bus So to read the value of TCRR correctly the first OCP read access has to be to the lower 16 bit offset 28h followed by OCP read access to the upper 16 bit offset 2Ah As the TCRR is updated using mo...

Page 1655: ...nization process These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged Figure 17 19 Timer Write Posted Status Register TWPS 31 16 Reserved...

Page 1656: ...TCAR1 register Note that since the OCP clock is completely asynchronous with the timer clock some synchronization is done in order to make sure that the TCAR1 value is not read while it is being updat...

Page 1657: ...bit resets all the function parts of the module During reads it always returns 0 0 Software reset is enabled 1 Software reset is disabled 0 Reserved 0 Reserved 17 3 17 Timer Capture Register TCAR2 Whe...

Page 1658: ...1658 Timers SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1659: ...is chapter describes the watchdog timer Topic Page 18 1 Introduction 1660 18 2 Architecture 1661 18 3 Low Level Programming Model 1667 18 4 Registers 1668 1659 SPRUGX9 15 April 2011 Watchdog Timer Sub...

Page 1660: ...d and not running 18 1 2 Functional Block Diagram Figure 18 1 shows a block diagram of the watchdog timer Figure 18 1 Watchdog Timer Block Diagram 18 1 3 Features The main features of the watchdog tim...

Page 1661: ...T WDT_WIRQENCLR 1 WDTINT Watchdog delay value DLY_IT_ENA reached 18 2 3 General Watchdog Timer Operation The watchdog timers are based on an upward 32 bit counter coupled with a prescaler The counter...

Page 1662: ...WD_OUT pin This pulse is one prescaled timer clock cycle wide and occurs at the same time as the timer counter overflow After reset generation the counter is automatically reloaded with the value sto...

Page 1663: ...ue of 1 clock divided by 2 and WDT_WCLR 5 PRE 1 clock divider enabled the reset period is as listed in Table 18 4 Table 18 4 Reset Period Examples WDT_WLDR Value Reset Period 0000 0000h 74 h 56 min FF...

Page 1664: ...SPR register have no effect on the start stop feature of the module 18 2 9 Modifying Timer Count Load Values and Prescaler Setting To modify the timer counter value the WDT_WCRR register prescaler rat...

Page 1665: ...the corresponding interrupt status bit is set in the watchdog status register WDT_WIRQSTAT and the output interrupt line is asserted active low when the flag EVENT_DLY and enable DLY_IT_ENA bits are...

Page 1666: ...s only to functional registers that require synchronization on from the timer functional clock domain WDTi_FCLK For write read operation the following registers are affected WDT_WCLR WDT_WCRR WDT_WLDR...

Page 1667: ...equence Watchdog Timer Module Global Initialization Table 18 7 lists the steps for initializing the watchdog timer module when the module is to be used for the first time Table 18 7 Watchdog Timer Mod...

Page 1668: ...bit access is not allowed and can corrupt register content NOTE The WDT_WISR and WDT_WIRQSTATRAW registers have the same functionality The WDT_WISR register is used for software backward compatibility...

Page 1669: ...escribed in the figure and table below This register controls the various parameters of the L4 interface Figure 18 5 WDT_WDSC Register 31 6 5 4 2 1 0 Reserved EMUFREE Reserved SOFTRESET Rsvd R 0 R W 0...

Page 1670: ...leted 18 4 4 WDT_WISR Register This register shows which interrupt events are pending inside the module It is shown and described in the figure and table below Figure 18 7 WDT_WISR Register 31 2 1 0 R...

Page 1671: ...gister The WDT_WCLR register controls the prescaler stage of the counter It is shown and descirbed in the figure and table below Figure 18 9 WDT_WCLR Register 31 6 5 4 2 0 Reserved PRE PTV Rsvd R 0 R...

Page 1672: ...the figure and table below Figure 18 11 WDT_WLDR Register 31 0 TIMER_LOAD R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 19 WDT_WLDR Register Field Descriptions Bits Field Descri...

Page 1673: ...g for register WDLY Read 0 No register write pending Read 1 Register write pending 4 W_PEND_WSPR Write pending for register WSPR Read 0 No register write pending Read 1 Register write pending 3 W_PEND...

Page 1674: ...eld Description 31 0 WDLY_VALUE Value of the delay register 18 4 12 WDT_WSPR Register The WDT_WSPR register holds the start stop value that controls the internal start stop FSM Figure 18 15 WDT_WSPR R...

Page 1675: ...R Read only n value after reset Table 18 24 WDT_WIRQSTATRAW Register Field Descriptions Bits Field Description 31 2 Reserved Write 0s for future compatibility Reads return 0 1 EVENT_DLY Settable raw s...

Page 1676: ...EGEND R W Read Write R Read only n value after reset Table 18 25 WDT_WIRQSTAT RegisterField Descriptions Bits Field Description 31 2 Reserved Write 0s for future compatibility Reads return 0 1 EVENT_D...

Page 1677: ...after reset Table 18 26 WDT_WIRQENSET Register Field Descriptions Bits Field Description 31 2 Reserved Write 0s for future compatibility Reads return 0 1 ENABLE_DLY Enable for delay event Read 0 Inte...

Page 1678: ...ue after reset Table 18 27 WDT_WIRQENCLR Register Field Descriptions Bits Field Description 31 2 Reserved Write 0s for future compatibility Reads return 0 1 ENABLE_DLY Enable for delay event Read 0 In...

Page 1679: ...nfiguration of the universal asynchronous receiver transmitter UART infrared data association IrDA consumer infrared CIR module Topic Page 19 1 Introduction 1680 19 2 Architecture 1682 19 3 Registers...

Page 1680: ...l and sleep mode Frequency prescaler values from 0 to 16383 to generate the appropriate baud rates Single 48 MHz clock reference for baud setting Two DMA requests 1 interrupt request to the system Bre...

Page 1681: ...MBAUD operations very fast infrared VFIR is not supported Framing error cyclic redundancy check CRC error illegal symbol FIR abort pattern SIR MIR detection 8 entry status FIFO with selectable trigge...

Page 1682: ...SD O SD mode is used to configure the transceivers The SD pin out is an inverted value of 1 ACREG 6 DSR I Data set ready Active low modem status signal Reading bit 5 of the modem status Unknown regis...

Page 1683: ...are flow control to manage transmission reception Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the...

Page 1684: ...SUME trigger level programmed via TCR 7 4 This reassertion requests the sending device to resume transmission 19 2 3 1 2 Auto CTS The transmitter circuitry checks CTS before sending the next data byte...

Page 1685: ...ger level programmed via TCR 7 4 NOTE If after an XOFF character has been sent software flow control is disabled the module transmits XON characters automatically to enable normal transmission to proc...

Page 1686: ...Here UART breaks are removed MDR1 7h Here UART is in reset or disabled Alternatively the SYSC 1 can be set to 1 to start a hardware reset from the generic synchronous reset module The reset progress c...

Page 1687: ...me data CRC 16 and ends with a stop flag C1h The bit format for a single word uses a single start bit eight data bits and one stop bit and is unaffected by the use and settings of the LCR register Not...

Page 1688: ...ssion Inserts a control escape CE byte preceding the byte Complements bit 5 of the byte that is exclusive ORs the byte with 20h The byte sent for the CRC computation is the initial byte written in the...

Page 1689: ...IRTX rises on the falling edge of the 7th 16XCLK On the falling edge of the 10th 16XCLK pulse IRTX falls creating a 3 clock wide pulse While TXD stays low a pulse is transmitted during the 7th to the...

Page 1690: ...packets the SIR Free Format mode is a sub function of the existing SIR mode such that all frames going to and from the FIFO buffers are untouched with respect to appending and removing control charac...

Page 1691: ...1 enable RHR interrupt Example 19 2 Transmit IrDA Transmit IrDA 6bytes frame with no parity baud rate 112 5Kbs FIFOs disabled 3 16 encoding MDR1 41h MDR1 2 0 001b SIR mode MDR1 6 1 SIP is generated au...

Page 1692: ...as frame abort CRC error or frame length error At the end of a frame reception the LH reads the line status register LSR to find out possible errors of received frame Data can be transferred both ways...

Page 1693: ...um is currently occupied When the SIPMODE bit of the mode definition register 1 MDR1 6 equals 1 the TX state machine always sends one SIP at the end of a transmission frame But when MDR1 6 0 the trans...

Page 1694: ...bytes frame with no parity baud rate 1 152 Mbs FIFOs disabled MDR1 04h MDR1 2 0 100b MIR mode LCR 82h LCR 7 1 access to write DLL and DLH LCR 1 0 10b set word length to 7 bits default 5 optional LCR 2...

Page 1695: ...able universal remote control By setting the MDR1 register the UART can be set to CIR mode in the same way as the other IrDA modes are set using the MDR1 register The CIR mode uses a variable pulse wi...

Page 1696: ...odulation length multiples of T is the method to distinguish between a 1 or a 0 The following SIRC digits show the difference in encoding between this and RC 5 for example NOTE The pulse width is exte...

Page 1697: ...ase to 7 bits This format is known as the extended RC 5 format The SIRC encoding uses the duration of modulation for mark and space hence the duration of data bits inside the standard frame length wil...

Page 1698: ...Carrier Modulation Looking closely at the actual modulation pulses of the infrared data stream each modulated pulse that constitutes a digit is a train of on off pulses see Figure 19 16 Figure 19 16...

Page 1699: ...s the CIR modulation duty cycles Figure 19 17 CIR Modulation Duty Cycle The transmission logic ensures that all pulses are transmitted completely that is no cutoff during transmission Furthermore whil...

Page 1700: ...IFO control register FCR and supplementary control register SCR Reading the TXFIFOFULL bit in SSR 0 as 1 means the FIFO is full The TLR register controls the FIFO trigger level which enables the DMA a...

Page 1701: ...source to the UART FIFO in transmit mode Note also that in the case of the UART flow control being enabled along with the interrupt capabilities the user must ensure that the UART flow control FIFO th...

Page 1702: ...Figure 19 22 Figure 19 23 and Figure 19 24 show the supported DMA operations In receive mode a DMA request is generated as soon as the receive FIFO reaches its threshold level defined in the trigger...

Page 1703: ...ro byte DMA active periods this does not represent the DMA signaling Example DMA disabled to show the end of the transfer Time 56 spaces uart 027 Preliminary www ti com Architecture Figure 19 21 Recei...

Page 1704: ...xample illustrates the setting of one space which uses the DMA for each transfer of one character to the transmit buffer see Figure 19 24 The buffer is filled at a faster rate than the BAUD rate trans...

Page 1705: ...f the transmission is signaled by the UARTi THR empty TX FIFO empty NOTE In IrDA mode the transmission is not ended immediately after the TX FIFO empties at which point there are still the last data b...

Page 1706: ...ttach end flags and properly terminate the frame 19 2 6 6 Store and Controlled Transmission SCT In SCT the LH first starts writing data into the TX FIFO Then after it writes a part of a frame for a bi...

Page 1707: ...ote that for the receiver line status interrupt RX_FIFO_STS bit LSR 7 generates the interrupt For the XOFF interrupt if a XOFF flow character detection caused the interrupt the interrupt is cleared by...

Page 1708: ...red but with an underrun error 2 Read IIR register OR 2 Transmission of the last bit of the IrDA frame completed successfully 6 Receiver line status CRC ABORT or frame length error is Read STATUS FIFO...

Page 1709: ...clocked using these clocks the power consumption is greatly reduced The module wakes up when any change is detected on the RX line if data is written to the TX FIFO when there is any change in the sta...

Page 1710: ...te generator and associated controls is shown in Figure 19 27 CAUTION It is mandatory that the MODESELECT bit in MDR1 2 0 7h disable before initializing or modifying clock parameter controls DLH and D...

Page 1711: ...h 04h 923 08 Kbps 0 16 1 843 Mbps 13x 2 00h 02h 1 846 Mbps 0 16 3 6884 Mbps 13 1 00h 01h 3 6923 Mbps 0 16 19 2 10 2 IrDA Baud Rates 48 MHz Clock Table 19 8 lists the IrDA baud rate settings Table 19 8...

Page 1712: ...ng the autobaud mode The following settings are detected in autobaud mode with a module clock of 48 MHz Speed 115 2k baud 57 6k baud 38 4k baud 28 8k baud 19 2k baud 14 4k baud 9 6k baud 4 8k baud 2 4...

Page 1713: ...3 XOFF1 TCR 3 XOFF1 TCR 3 1Ch SPR TLR 3 SPR TLR 3 SPR TLR 3 SPR TLR 3 XOFF2 TLR 3 XOFF2 TLR 3 20h MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 24h MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 28h SFLSR TXFLL SFLSR TXFLL SFLSR TXFL...

Page 1714: ...Bit Field Value Description 15 8 Reserved 0 Reserved 7 0 RHR 0 FFh Receive holding register 19 3 2 Transmit Holding Register THR The transmitter section consists of the transmit holding register and...

Page 1715: ...escriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 CTSIT Can be written only when EFR 4 1 0 Disables the CTS interrupt 1 Enables the CTS interrupt 6 RTSIT Can be written only when EFR...

Page 1716: ...R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 13 IrDA Interrupt Enable Register IER Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 EOFIT 0...

Page 1717: ...Enable Register IER 15 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved TXSTATUSIT Reserved RXOVERRUNIT RXSTOPIT THRIT RHRIT R 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value aft...

Page 1718: ...t Identification Register IIR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 6 FCR_MIRROR 0 3h Mirror the contents of FCR 0 on both bits 5 1 IT_TYPE 0 1Fh Seven possible int...

Page 1719: ...ntification Register IIR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 EOF_IT 0 Received EOF interrupt inactive 1 Received EOF interrupt active 6 LINE_STS_IT 0 Receiver lin...

Page 1720: ...STOPIT THRIT RHRIT R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 17 CIR Interrupt Identification Register IIR Field Descriptions Bit Field Value Descriptio...

Page 1721: ...d TLR 3 0 0000 TX_FIFO_TRIG is not considered If SCR 6 1 TX_FIFO_TRIG is 2 LSB of the trigger level 1 to 63 on 6 bits with a granularity of 1 If SCR 6 0 and TLR 3 0 0000 0 8 characters 1h 16 character...

Page 1722: ...d to 0 and remains in this state as long as LCR 6 1 0 Normal operating condition 1 Forces the transmitter output to go low to alert the communication terminal 5 PARITY_TYPE2 If LCR 3 1 0 If LCR 5 0 LC...

Page 1723: ...XON any function 1 Enable XON any function 4 LOOPBACKEN Loopback mode enable 0 Normal operating mode 1 Enable local loopback mode internal In this mode the MCR 3 0 signals are looped back into MSR 7...

Page 1724: ...erved 7 RXFIFOSTS 0 Normal operation 1 At least one parity error framing error or break indication in the RX FIFO Bit 7 is cleared when no errors are present in the RX FIFO 6 TXSRE 0 Transmitter hold...

Page 1725: ...tain the last byte of the frame to be read 1 The RX FIFO RHR contains the last byte of the frame to be read This bit is set to 1 only when the last byte of a frame is available to be read It is used t...

Page 1726: ...on 15 8 Reserved 0 Reserved 7 THREMPTY 0 Transmit holding register TX FIFO is not empty 1 Transmit hold register TX FIFO is empty The transmission is not necessarily completed 6 Reserved 0 Reserved 5...

Page 1727: ...D_STS This bit is the complement of the DCD input In loopback mode it is equivalent to MCR 3 6 NRI_STS This bit is the complement of the RI input In loopback mode it is equivalent to MCR 2 5 NDSR_STS...

Page 1728: ...gure 19 43 Transmission Control Register TCR 15 8 7 4 3 0 Reserved RXFIFOTRIGSTART RXFIFOTRIGHALT R 0 R W 0 R W Fh LEGEND R W Read Write R Read only n value after reset Table 19 25 Transmission Contro...

Page 1729: ...60 characters 0 0000 Defined by TLR 7 4 from 4 to 60 characters with a granularity of 4 characters 1 any value Defined by the concatenated value of TLR 7 4 and FCR 7 6 from 1 to 63 characters with a...

Page 1730: ...Table 19 30 Mode Definition Register 1 MDR1 Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 FRAMEENDMODE IrDA mode only 0 Frame length method 1 Set EOT bit method 6 SIPMODE M...

Page 1731: ...ALT Provides alternate functionality for MDR1 4 0 Normal mode 1 Alternate mode for SETTXIR 6 IRRXINVERT Only for IR mode IrDA and CIR Invert RX pin in the module before the voting or sampling system l...

Page 1732: ...d 4 OE_ERROR 0 No error 1 Overrun error in RX FIFO when frame at top of RX FIFO was received 3 FRAME_TOO_LONG_ERROR 0 No error 1 Frame length too long error in frame at top of RX FIFO 2 ABORT_DETECT 0...

Page 1733: ...0 Reserved 7 0 SFREGL 0 FFh LSB part of the frame length 19 3 24 Status FIFO Register High SFREGH The frame lengths of received frames are written into the status FIFO This information can be read by...

Page 1734: ...ster BLR is shown in Figure 19 52 and described in Table 19 36 Figure 19 52 BOF Control Register BLR 15 8 7 6 5 0 Reserved STSFIFORESET XBOFTYPE Reserved R 0 R W 0 R W 1 R 0 LEGEND R W Read Write R Re...

Page 1735: ...rs 0 SD pin is set to high 1 SD pin is set to low 5 DISIRRX Disable RX input 0 Normal operation RX input automatically disabled during transmit but enabled outside of transmit operation 1 Disables RX...

Page 1736: ...5 8 Reserved 0 Reserved 7 RXTRIGGRANU1 0 Disables the granularity of 1 for trigger RX level 1 Enables the granularity of 1 for trigger RX level 6 TXTRIGGRANU1 0 Disables the granularity of 1 for trigg...

Page 1737: ...pplementary Status Register SSR Field Descriptions Bit Field Value Description 15 3 Reserved 0 Reserved 2 DMACOUNTERRST 0 The DMA counter will not be reset if the corresponding FIFO is reset via FCR 1...

Page 1738: ...in reception state which is disabled by setting the ACREG 5 bit to 1 The BOF length register EBLR is shown in Figure 19 56 and described in Table 19 40 NOTE If the RX_STOP interrupt occurs before a by...

Page 1739: ...ure 19 57 Module Version Register MVR 15 8 7 4 3 0 Reserved MAJORREV MINORREV R 0 R unknown R unknown LEGEND R W Read Write R Read only n value after reset Table 19 41 Module Version Register MVR Fiel...

Page 1740: ...iven based in the internal activity of the module 3h Smart idle Wakeup Acknowledgement to an idle request is given based in the internal activity of the module The module is allowed to generate wakeup...

Page 1741: ...ster WER Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 TXWAKEUPEN Wake up interrupt 0 Event is not allowed to wake up the system 1 Event can wake up the system Event can be...

Page 1742: ...12 BAUD multiple The carrier frequency prescaler register CFPS is shown in Figure 19 61 and described in Table 19 45 Figure 19 61 Carrier Frequency Prescaler Register CFPS 15 8 7 0 Reserved CFPS R 0...

Page 1743: ...0 FFh Divisor latches low Stores the 8 LSB divisor value 19 3 36 Divisor Latches High Register DLH The divisor latches high register DLH with the DLL register stores the 14 bit divisor for generation...

Page 1744: ...able bit UART mode only 0 Normal operation 1 Auto RTS flow control is enabled RTS pin goes high inactive when the receiver FIFO HALT trigger level TCR 3 0 is reached and goes low active when the recei...

Page 1745: ...9 50 Figure 19 65 XON1 ADDR1 Register 15 8 7 0 Reserved XONWORD1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 50 XON1 ADDR1 Register Field Descriptions Bit Field Value Desc...

Page 1746: ...OFFWORD1 0 Stores the 8 bit XOFF1 character in UART modes 19 3 41 XOFF2 Register In UART mode XOFF2 character The XOFF2 register is shown in Figure 19 68 and described in Table 19 53 Figure 19 68 XOFF...

Page 1747: ...XFLL 0 FFh LSB register used to specify the frame length 19 3 43 Transmit Frame Length High Register TXFLH The transmit frame length high register TXFLH and the TXFLL register hold the 13 bit transmit...

Page 1748: ...SB register used to specify the frame length in reception 19 3 45 Received Frame Length High Register RXFLH The received frame length high register RXFLH and the RXFLL register hold the 12 bit receive...

Page 1749: ...0 UART in standard mode Usage limitation Only 7 and 8 bits character 5 and 6 bits not supported 7 bits character with space parity not supported Baud rate between 1200 and 115 200 bp s 10 possibiliti...

Page 1750: ...1750 UART IrDA CIR Module SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1751: ...rable as Host or Device Even though both ports are made of OTG Controllers OTG feature is not supported The two ports operate independent of each other Topic Page 20 1 Introduction 1752 20 2 Architect...

Page 1752: ...are the CPPI DMA controller and accompanying Queue Manager Interrupt Pacer Power Management module and PHY UTMI clock Within the descriptions of the USB subsystem that would follow the term USB contro...

Page 1753: ...e Supports high bandwidth ISO mode Supports 15 Transmit Tx and 15 Receive Rx Endpoints including Endpoint 0 Includes a 32KB Endpoint FIFO RAM per Module 64Kbytes per USB Subsystem with user programmab...

Page 1754: ...d device capabilities but is not capable of changing roles device host on the fly 20 1 5 Functional Block Diagram Figure 1 displays a high level functional block diagram covering the major blocks of t...

Page 1755: ...ry map The enabling or masking of the interrupt is controlled via software Writing 1 s WR1 to either the IRQENABLE_SET or IRQENABLE_CLR addresses will enable or disable the interrupt respectively An E...

Page 1756: ...r can be configured to use the same FIFO for example to reduce the size of RAM block needed provided they can never be active at the same time The role host or device that the USB controller assumes i...

Page 1757: ...15KOhms resistors When assuming the role of a device the required 1 5Kohm pull up resistor on the D line is enabled automatically to signify the USB capability to the external host as a FS device HS o...

Page 1758: ...In other words Index Register region behaves as a proxy to access a selected endpoint registers Non indexed Endpoint Control Status Register Space These regions are dedicated endpoint registers memor...

Page 1759: ...f a host What this means is that the USB cable end connector will not be able to control the role of the OTG controller and the user needs to be aware of the firmware program setting prior to performi...

Page 1760: ...If the Suspend interrupt has been enabled an interrupt will be generated at this time At this point the controller can then be left active and hence able to detect when Resume signaling occurs on the...

Page 1761: ...dress value contained in the command should be written to the FADDR register at the completion of the command The PERI_CSR0 register should be written by setting the SERV_RXPKTRDY bit bit 6 indicating...

Page 1762: ...data the controller will send a STALL to tell the host that the request was not executed An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSR0 bit 2 will be set If the host send...

Page 1763: ...and RX corresponding to the different phases of the control transfer and the states endpoint 0 enters for the different phases of the transfer described in later sections The default mode on power up...

Page 1764: ...Load FIFO Set TxPktRdy Load FIFO Set TxPktRdy Set DataEnd Unload Device Req Clear RxPktRdy CPU actions UnLoad FIFO Clear RxPktRdy Unload Device Req Clear RxPktRdy Unload FIFO Clear RxPktRdy Unload FI...

Page 1765: ...e the next action taken depends on the endpoint state If endpoint 0 is in IDLE state the only valid reason an interrupt can be generated is as a result of the controller receiving data from the bus Th...

Page 1766: ...r of Peripheral Mode IDLE mode is the mode the Endpoint 0 control needs to select at power on or reset and is the mode to which the Endpoint 0 control should return when the RX and TX modes are termin...

Page 1767: ...valid token causing a SETUPEND condition bit 4 of PERI_CSR0 is set 2 The firmware sends a packet containing less than the maximum packet size for Endpoint 0 3 The firmware sends an empty data packet U...

Page 1768: ...a SETUPEND condition setting bit 4 of PERI_CSR0 2 The host sends a packet which contains less than the maximum packet size for endpoint 0 3 The host sends an empty data packet Until the transaction i...

Page 1769: ...ort the current transfer because it cannot process the command or has some other internal error then it should set the SENDSTALL bit bit 5 of PERI_CSR0 The controller will then send a STALL packet to...

Page 1770: ...ndpoint and the PERI_TXCSR register DMAEN and DMAMODE bit fields should be set when using DMA Table 20 2 displays the PERI_TXCSR setting when used for Bulk transfer Table 20 2 PERI_TXCSR Register Bit...

Page 1771: ...sing the CPPI DMA A separate section detailing the use of the DMA is discussed within a latter section Suffix is to say that the PERI_TXCSR DMAEN and DMAMODE bit fields need to be set and the PERI_TXC...

Page 1772: ...n the FIFO indicated by the RXPKTRDY bit bit 0 of PERI_RXCSR being set they should be flushed by setting the FLUSHFIFO bit bit 4 of PERI_RXCSR NOTE It may be necessary to set this bit twice in success...

Page 1773: ...This means that the controller should never respond with a NYET handshake only ACK NAK STALL To ensure this the DISNYET bit in the PERI_RXCSR register bit 12 should be set to disable the transmission...

Page 1774: ...0 in the same way as for a Bulk Tx endpoint As the interrupt could occur almost any time within a frame microframe depending on when the host has scheduled the transaction this may result in irregular...

Page 1775: ...will be generated whenever the endpoint has a packet in its FIFO This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention However this featur...

Page 1776: ...derruns 20 3 1 4 2 3 Isochronous OUT Error Handling Peripheral Mode If there is no space in the FIFO to store a packet when it is received from the host the OVERRUN bit in the PERI_RXCSR register bit...

Page 1777: ...e application requires the controller to leave suspend mode it needs to clear the SUSPENDM bit in the POWER register set the RESUME bit and leave it set for 20ms While the RESUME bit is high the contr...

Page 1778: ...new address 20 3 2 1 1 Setup Phase of Control Transaction Host Mode For the SETUP Phase of a control transaction Figure 20 7 the software driving the USB host device needs to 1 Load the 8 bytes of the...

Page 1779: ...ented Transaction Complete Implies Problem at Peripheral End of Connection Transaction Deemed Completed Error Bit Set TxPktRdy Cleared Error Count Cleared Interrupt Generated Yes Error Count 3 TxPktRd...

Page 1780: ...to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longe...

Page 1781: ...ACK Sent RxPktRdy Set Transaction Complete Implies Problem at Peripheral End of Connection Transaction Deemed Completed Error Bit Set ReqPkt Cleared Error Count Cleared Interrupt Generated Yes Error...

Page 1782: ...sued a STALL response If ERROR bit is set it means that the controller has tried to send the OUT token and the following data packet three times without getting any response If NAK_TIMEOUT is set it m...

Page 1783: ...ented Transaction Complete Implies Problem at Peripheral End of Connection Transaction Deemed Completed Error Bit Set TxPktRdy Cleared Error Count Cleared Interrupt Generated Yes Error Count 3 TxPktRd...

Page 1784: ...bit 2 the ERROR bit bit 4 the NAK_TIMEOUT bit bit 7 or RXPKTRDY bit bit 0 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL respo...

Page 1785: ...nted ACK Sent RxPktRdy Set Transaction Complete Implies Problem at Peripheral End of Connection Transaction Deemed Completed Error Bit Set ReqPkt Cleared Error Count Cleared Interrupt Generated Yes Er...

Page 1786: ...ether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL re...

Page 1787: ...and StatusPkt Both Set No Yes OUT Token Sent Command Could Not Be Completed Yes No Yes Zero Length DATA1 Packet Sent STALL Received ACK Received RxStall Set TxPktRdy Cleared Error Count Cleared Interr...

Page 1788: ...ransfer Endpoint Number of the target device in RENDPN field This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration The RXMAXP register fo...

Page 1789: ...gain by clearing the DATAERR_NAKTIMEOUT bit or to abort the transaction by clearing REQPKT bit before clearing the DATAERR_NAKTIMEOUT bit The packets received should not exceed the size specified in t...

Page 1790: ...re of the user application in automatically setting the TXPKTRDY bit when servicing transactions using CPU Note If DMA is needs to be used in place of the CPU the following table displays the setting...

Page 1791: ...ll send a STALL response This is indicated by the RXSTALL bit of HOST_TXCSR register bit 5 being set 20 3 2 3 Interrupt Transfer Host Mode When the controller is operating as the host interactions wit...

Page 1792: ...roframe The relevant interrupt enable bit in the INTRRXE register should be set if an interrupt is required for this endpoint The following bits of HOST_RXCSR register should be set as Clear AUTOCLEAR...

Page 1793: ...other packet in its FIFO This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with isochron...

Page 1794: ...nerated whenever a packet is sent and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register bit 0 in the same way as for a Bulk...

Page 1795: ...e CDMA Scheduler when queues are empty or full CPPI DMA CDMA The CDMA is responsible for transferring data between the CPPI FIFO and Main Memory It acquires free Buffer Descriptor from the QM Receive...

Page 1796: ...ue is a hardware managed list of available descriptors with pre linked empty buffers that are to be used by the receive ports for host type descriptors Free Descriptor Buffer Queues are implemented by...

Page 1797: ...llocated size of the descriptors is application dependent Port will make use of the first 32 bytes only From a general USB use perspective a 32 byte descriptor size is suffix and the use of this size...

Page 1798: ...of the packet without transferring data For transmit if a packet has this bit set the XDMA will ignore the CPPI packet size and send a zero length packet to the USB controller This field contains prot...

Page 1799: ...e actual 21 0 Original buffer 0 pointer buffer location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is necess...

Page 1800: ...plete This field is not altered by 13 12 Packet return queue mgr the DMA during transmission or reception and is initialized by the CPU There is only 1 queue manager in the USB HS FS device controller...

Page 1801: ...r location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is necessary to permanently store the buffer pointer i...

Page 1802: ...ushFIFO bit in the Mentor USB controller Tx RxCSR register must be set The following is the Transmit teardown procedure highlighting the steps required to be followed 1 Set the TX_TEARDOWN bit in the...

Page 1803: ...queues exist a total of 156 queues within the CPPI 4 1 DMA Regardless of the type of queue queues are used to hold pointers to Packet or Buffer Descriptors while they are being passed between the Hos...

Page 1804: ...x Endpoint 14 90 2 USB1 Tx Endpoint 15 92 1 Reserved 93 1 USB0 Tx Endpoint 1 completion queue 94 1 USB0 Tx Endpoint 2 completion queue 95 1 USB0 Tx Endpoint 3 completion queue 96 1 USB0 Tx Endpoint 4...

Page 1805: ...dpoint 7 completion queue 132 1 USB1 Tx Endpoint 8 completion queue 133 1 USB1 Tx Endpoint 9 completion queue 134 1 USB1 Tx Endpoint 10 completion queue 135 1 USB1 Tx Endpoint 11 completion queue 136...

Page 1806: ...ased on the endpoint number used For USB0 transmit endpoints 1 to 15 Queues 92 up to queue 106 are reserved assigned for use as a completion queue respectively Similarly for USB1 transmit endpoints 1...

Page 1807: ...o be allocated depends on the total number of descriptors defined within all memory regions A minimum of four bytes of memory needs to be allocated for each Descriptor defined within all 16 memory reg...

Page 1808: ...channel talks to has free space on TX FIFO full signal is not asserted or a valid block on Rx FIFO empty signal is not asserted 3 If the DMA channel is capable of processing a credit to transfer a bl...

Page 1809: ...ill only service the first three entries in a round robin fashion checking each credited endpoint for transfer one after the other and servicing the endpoint that has data to transfer Case 2 Enabled e...

Page 1810: ...r the Endpoint field in use is programmed for Transparent Mode i e TXMODE0 1 TXn_MODE 00b and RXMODE0 1 RXn_MODE 00b 20 4 8 2 RNDIS DMA Transfer RNDIS mode DMA is used for large transfers i e total da...

Page 1811: ...to program the USB module to transfer data that is an exact multiple of the USB MaxPktSize Tx RxMaxP programmed value without having to send an additional short packet to terminate NOTE As in RNDIS m...

Page 1812: ...cessary steps required to perform a USB data transfer using the CPPI 4 1 DMA is expressed using an example for both transmit and receive cases Assume USB0 is ready to perform a USB data transfer of si...

Page 1813: ...The receive setup is as follows Two buffer descriptors with 256 bytes of data buffer size One buffer descriptor with 96 bytes can be greater of data buffer size Within the rest of this section the fo...

Page 1814: ...nsmit Initialization Step 1 The CPU performs the following steps for transmit initialization 1 Initializes Memory Region 0 base address and Memory Region 0 size Link RAM0 Base address Link RAM0 data s...

Page 1815: ...e data to be transferred in main memory to the CPPI FIFO b The XDMA sees FIFO_empty not asserted and transfers 64 byte block from CPPI FIFO to Endpoint FIFO c The CDMA performs the above 2 steps a and...

Page 1816: ...us of the TXSQ empty to the CDMAS and the TXCQ to the CPU via an interrupt 20 4 9 2 Receive USB Data Flow Using DMA The receive buffer descriptors and queue status configuration prior to the transfer...

Page 1817: ...fer Descriptor 2 Buffer Buffer pointer Next descriptor pointer Buffer size 256 Buffer pointer Next descriptor pointer Buffer size 256 Tail Tail Preliminary www ti com Communications Port Programming I...

Page 1818: ...channel 3 The CDMA will then begin writing the 64 byte block of packet data into this DB 4 The CDMA will continue filling the buffer with additional 64 byte blocks of data from the CPPI FIFO and will...

Page 1819: ...mode in which it transmits a continuous J on the bus 20 5 3 TEST_K To enter the Test_K test mode the software should set the TEST_K bit in the TESTMODE register to 1 The USB controller will then go in...

Page 1820: ...w be read out of the Rx FIFO 20 5 6 FORCE_HOST The Force Host test mode enables you to instruct the core to operate in Host mode regardless of whether it is actually connected to any peripheral that i...

Page 1821: ...a internal logic Software can set or clear the register by accessing the appropriate locations in the memory map The enabling or masking of the interrupt is controlled via software Writing 1 s WR1 to...

Page 1822: ...nterrupt Groupings Interrupt CPPI DMA Packet Completion Grouping EP Description tx_pkt_cmp_0 1 2 15 USB0 Tx CPPI DMA Packet completion status rx_pkt_cmp_0 1 2 15 USB0 Rx CPPI DMA Packet completion sta...

Page 1823: ...pletions will have a frame counter frame threshold and frame enable If the frame counter exceeds the frame threshold then an interrupt will be generated This assumes the frame enable counter has been...

Page 1824: ...lts and transfer the data to the F_REGS module The F_REGS module will generate the hardware IRQ event source Interrupts for TX_ENDP 15 0 and RX_ENDP 15 1 are not generated when both DMAReqEnab and DMA...

Page 1825: ...core documentation for more details on these interrupts Interrupt USB 8 is generated outside the Mentor core by the interrupt sub module whenever the level of DRVVBUS changes This is usually due to en...

Page 1826: ...he corresponding interrupt source in the USB Interrupt Source register The USB Interrupt Mask Set register allows writing a 1 in bit positions to enable the corresponding interrupt source Those bits w...

Page 1827: ...FIG 20h EOI USBSS IRQ_EOI 24h IRQSTATRAW USBSS IRQ_STATUS_RAW 28h IRQSTAT USBSS IRQ_STATUS 2Ch IRQENABLER USBSS IRQ_ENABLE_SET 30h IRQCLEARR USBSS IRQ_ENABLE_CLR 100h IRQDMATHOLDTX00 USBSS IRQ_DMA_THR...

Page 1828: ...OLD_RX1_3 240h IRQFRAMEENABLE0 USBSS IRQ_FRAME_ENABLE_0 244h IRQFRAMEENABLE1 USBSS IRQ_FRAME_ENABLE_1 20 9 1 1 USBSS Revision Register REVREG The USBSS revision register REVREG contains the major and...

Page 1829: ...cp en_n phy1 utmi en_n R 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 Reserved Standby mode Idlemode Freeemu Soft reset R 0 R W 2h R W 2h R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset...

Page 1830: ...de 3 Smart idle wakeup capable mode 1 Freeemu Sensitivity to emulation debug suspend input signal 0 Sensitive to emulation suspend 1 NOT sensitive to emulation suspend 0 Soft reset Software reset of U...

Page 1831: ...t has been written to The USBSS end of interrupt register is shown in Figure 20 24 and described in Table 20 34 Figure 20 24 USBSS End of Interrupt Register EOI 31 16 Reserved R 0 15 1 0 Reserved EOI_...

Page 1832: ...ble 20 35 USBSS IRQ_STATUS_RAW IRQSTATRAW Field Descriptions Bits Field Description 31 12 Reserved Always read as 0 Writes have no effect 11 rx_pkt_cmp_1 Interrupt status for USB1 Rx CPPI DMA packet c...

Page 1833: ...et Table 20 36 USBSS IRQ_STATUS IRQSTAT Field Descriptions Bits Field Description 31 12 Reserved Always read as 0 Writes have no effect 11 rx_pkt_cmp_1 Interrupt status for USB1 Rx CPPI DMA packet com...

Page 1834: ...able 20 37 USBSS IRQ_ENABLE_SET Register IRQENABLER Field Descriptions Bits Field Description 31 12 Reserved Always read as 0 Writes have no effect 11 rx_pkt_cmp_1 Interrupt enable for USB1 Rx CPPI DM...

Page 1835: ...er reset Table 20 38 USBSS IRQ_ENABLE_CLR Register IRQCLEARR Field Descriptions Bits Field Description 31 12 Reserved Always read as 0 Writes have no effect 11 rx_pkt_cmp_1 Interrupt enable for USB1 R...

Page 1836: ...TX0_0 register is shown in Figure 20 29 and described in Table 20 39 Figure 20 29 USBSS IRQ_DMA_THRESHOLD_TX0_0 Register IRQDMATHOLDTX00 31 24 23 16 15 8 7 0 dma_thres_tx0_3 dma_thres_tx0_2 dma_thres_...

Page 1837: ...threshold value for tx_pkt_cmp_0 for USB0 endpoint 4 20 9 1 10 USBSS IRQ_DMA_THRESHOLD_TX0_2 Register IRQDMATHOLDTX02 The USBSS IRQ_DMA_THRESHOLD_TX0_2 register IRQDMATHOLDTX02 defines the size of th...

Page 1838: ...13 7 0 dma_thres_tx0_ DMA threshold value for tx_pkt_cmp_0 for USB0 endpoint 12 12 20 9 1 12 USBSS IRQ_DMA_THRESHOLD_RX0_0 Register IRQDMATHOLDRX00 The USBSS IRQ_DMA_THRESHOLD_RX0_0 register IRQDMATHO...

Page 1839: ...res_rx0_4 DMA threshold value for rx_pkt_cmp_0 for USB0 endpoint 4 20 9 1 14 USBSS IRQ_DMA_THRESHOLD_RX0_2 Register IRQDMATHOLDRX02 The USBSS IRQ_DMA_THRESHOLD_RX0_2 register defines the size of the f...

Page 1840: ...res_rx0_12 DMA threshold value for rx_pkt_cmp_0 for USB0 endpoint 12 20 9 1 16 USBSS IRQ_DMA_THRESHOLD_TX1_0 Register IRQDMATHOLDTX10 The USBSS IRQ_DMA_THRESHOLD_TX1_0 register IRQDMATHOLDTX10 defines...

Page 1841: ...A threshold value for tx_pkt_cmp_0 for USB1 endpoint 4 20 9 1 18 USBSS IRQ_DMA_THRESHOLD_TX1_2 Register IRQDMATHOLDTX12 The USBSS IRQ_DMA_THRESHOLD_TX1_2 register IRQDMATHOLDTX12 defines the size of t...

Page 1842: ...3 7 0 dma_thres_tx1_12 DMA threshold value for tx_pkt_cmp_0 for USB1 endpoint 12 20 9 1 20 USBSS IRQ_DMA_THRESHOLD_RX1_0 Register IRQDMATHOLDRX10 The USBSS IRQ_DMA_THRESHOLD_RX1_0 register IRQDMATHOLD...

Page 1843: ...A threshold value for rx_pkt_cmp_0 for USB1 endpoint 4 20 9 1 22 USBSS IRQ_DMA_THRESHOLD_RX1_2 Register IRQDMATHOLDRX12 The USBSS IRQ_DMA_THRESHOLD_RX1_2 register IRQDMATHOLDRX12 defines the size of t...

Page 1844: ...Figure 20 44 and described in Table 20 54 Figure 20 44 USBSS IRQ_DMA_THRESHOLD_RX1_3 Register IRQDMATHOLDRX13 31 24 23 16 15 8 7 0 dma_thres_rx1_15 dma_thres_rx1_14 dma_thres_rx1_13 dma_thres_rx1_12...

Page 1845: ...ribed in Table 20 55 Figure 20 45 USBSS IRQ_DMA_ENABLE_0 Register IRQDMAENABLE0 31 18 17 16 dma_en_rx0_15 dma_en_rx0_1 Reserv ed R W 0 R 0 15 3 2 1 0 dma_en_tx0_15 dma_en_tx0_2 dma_en_tx0_1 Reserv ed...

Page 1846: ...DMA_ENABLE_0 Register is shown in Figure 20 46 and described in Table 20 56 Figure 20 46 USBSS IRQ_DMA_ENABLE_1 Register IRQDMAENABLE1 31 18 17 16 dma_en_rx1_15 dma_en_rx1_1 Rsvd R W 0 R 0 15 2 1 0 dm...

Page 1847: ...read as 0 Writes have no effect 20 9 1 27 USBSS IRQ_FRAME_THRESHOLD_TX0_1 Register IRQFRAMETHOLDTX01 The USBSS IRQ_FRAME_THRESHOLD_TX0_1 register IRQFRAMETHOLDTX01 defines the size of the four FRAME...

Page 1848: ...E threshold value for tx_pkt_cmp_0 for USB1 endpoint 8 20 9 1 29 USBSS IRQ_FRAME_THRESHOLD_TX0_3 Register IRQFRAMETHOLDTX03 The USBSS IRQ_FRAME_THRESHOLD_TX0_3 register IRQFRAMETHOLDTX03 defines the s...

Page 1849: ...lways read as 0 Writes have no effect 20 9 1 31 USBSS IRQ_FRAME_THRESHOLD_RX0_1 Register IRQFRAMETHOLDRX01 The USBSS IRQ_FRAME_THRESHOLD_RX0_1 register IRQFRAMETHOLDRX01 defines the size of the four F...

Page 1850: ...E threshold value for rx_pkt_cmp_0 for USB1 endpoint 8 20 9 1 33 USBSS IRQ_FRAME_THRESHOLD_RX0_3 Register IRQFRAMETHOLDRX03 The USBSS IRQ_FRAME_THRESHOLD_RX0_3 register IRQFRAMETHOLDRX03 defines the s...

Page 1851: ...ys read as 0 Writes have no effect 20 9 1 35 USBSS IRQ_FRAME_THRESHOLD_TX1_1 Register IRQFRAMETHOLDTX11 The USBSS IRQ_FRAME_THRESHOLD_TX1_1 register IRQFRAMETHOLDTX11 defines the size of the four FRAM...

Page 1852: ...E threshold value for tx_pkt_cmp_0 for USB1 endpoint 8 20 9 1 37 USBSS IRQ_FRAME_THRESHOLD_TX1_3 Register IRQFRAMETHOLDTX13 The USBSS IRQ_FRAME_THRESHOLD_TX1_3 register IRQFRAMETHOLDTX13 defines the s...

Page 1853: ...lways read as 0 Writes have no effect 20 9 1 39 USBSS IRQ_FRAME_THRESHOLD_RX1_1 Register IRQFRAMETHOLDRX11 The USBSS IRQ_FRAME_THRESHOLD_RX1_1 register IRQFRAMETHOLDRX11 defines the size of the four F...

Page 1854: ...E threshold value for rx_pkt_cmp_0 for USB1 endpoint 8 20 9 1 41 USBSS IRQ_FRAME_THRESHOLD_RX1_3 Register IRQFRAMETHOLDRX13 The USBSS IRQ_FRAME_THRESHOLD_RX1_3 register IRQFRAMETHOLDRX13 defines the s...

Page 1855: ...frame count has exceeded the threshold or not The USBSS IRQ_FRAME_ENABLE_0 register is shown in Figure 20 63 and described in Table 20 73 Figure 20 63 USBSS IRQ_FRAME_ENABLE_0 Register IRQFRAMEENABLE...

Page 1856: ...frame count has exceeded the threshold or not The USBSS IRQ_FRAME_ENABLE_1 register is shown in Figure 20 64 and described in Table 20 74 Figure 20 64 USBSS IRQ_FRAME_ENABLE_1 Register IRQFRAMEENABLE...

Page 1857: ...ISEP1 USB0 Generic RNDIS Size EP1 1084h USB0GENRNDISEP2 USB0 Generic RNDIS Size EP2 1088h USB0GENRNDISEP3 USB0 Generic RNDIS Size EP3 108Ch USB0GENRNDISEP4 USB0 Generic RNDIS Size EP4 1090h USB0GENRND...

Page 1858: ...1 R 0 0 R 0 0 R 0 0 LEGEND R W Read Write R Read only n value after reset Table 20 76 USB0 Revision Register USB0REV Field Descriptions Bits Field Value Description 31 30 Scheme Used to distinguish be...

Page 1859: ...ue after reset Table 20 77 USB0 Control Register USB0CTRL Field Descriptions Bits Field Value Description 31 dis_deb Disable the VBUS debouncer circuit fix 30 dis_srp Disable the OTG Session Request P...

Page 1860: ...optimizes software accesses in a module where a large number of events are associated to one IRQ line The merged status is read only and does not need to be actively cleared like the IRQ status It wi...

Page 1861: ...r it has been written to The USB0 IRQ_EOI register is shown in Figure 20 69 and described in Table 20 80 Figure 20 69 USB0 IRQ_EOI Register USB0IRQEOI 31 1 1 0 Reserved EOI for USB0 R 0 R W 0 LEGEND R...

Page 1862: ...B0IRQSTATRAW0 Field Descriptions Bits Field Description 31 RX EP 15 Interrupt status for RX endpoint 15 30 RX EP 14 Interrupt status for RX endpoint 14 29 RX EP 13 Interrupt status for RX endpoint 13...

Page 1863: ...4 TX EP 4 Interrupt status for TX endpoint 4 3 TX EP 3 Interrupt status for TX endpoint 3 2 TX EP 2 Interrupt status for TX endpoint 2 1 TX EP 1 Interrupt status for TX endpoint 1 0 TX EP 0 Interrupt...

Page 1864: ...endpoint 14 29 TX FIFO 13 Interrupt status for TX FIFO endpoint 13 28 TX FIFO 12 Interrupt status for TX FIFO endpoint 12 27 TX FIFO 11 Interrupt status for TX FIFO endpoint 11 26 TX FIFO 10 Interrupt...

Page 1865: ...ld Descriptions Bits Field Description 31 RX EP 15 Interrupt status for RX endpoint 15 30 RX EP 14 Interrupt status for RX endpoint 14 29 RX EP 13 Interrupt status for RX endpoint 13 28 RX EP 12 Inter...

Page 1866: ...X EP 4 Interrupt status for TX endpoint 4 3 TX EP 3 Interrupt status for TX endpoint 3 2 TX EP 2 Interrupt status for TX endpoint 2 1 TX EP 1 Interrupt status for TX endpoint 1 0 TX EP 0 Interrupt sta...

Page 1867: ...FIFO 13 Interrupt status for TX FIFO endpoint 13 28 TX FIFO 12 Interrupt status for TX FIFO endpoint 12 27 TX FIFO 11 Interrupt status for TX FIFO endpoint 11 26 TX FIFO 10 Interrupt status for TX FI...

Page 1868: ...ield Descriptions Bits Field Description 31 RX EP 15 Interrupt enable for RX endpoint 15 30 RX EP 14 Interrupt enable for RX endpoint 14 29 RX EP 13 Interrupt enable for RX endpoint 13 28 RX EP 12 Int...

Page 1869: ...Bits Field Description 3 TX EP 3 Interrupt enable for TX endpoint 3 2 TX EP 2 Interrupt enable for TX endpoint 2 1 TX EP 1 Interrupt enable for TX endpoint 1 0 TX EP 0 Interrupt enable for TX endpoin...

Page 1870: ...X FIFO endpoint 14 29 TX FIFO 13 Interrupt enable for TX FIFO endpoint 13 28 TX FIFO 12 Interrupt enable for TX FIFO endpoint 12 27 TX FIFO 11 Interrupt enable for TX FIFO endpoint 11 26 TX FIFO 10 In...

Page 1871: ...ield Descriptions Bits Field Description 31 RX EP 15 Interrupt enable for RX endpoint 15 30 RX EP 14 Interrupt enable for RX endpoint 14 29 RX EP 13 Interrupt enable for RX endpoint 13 28 RX EP 12 Int...

Page 1872: ...Bits Field Description 3 TX EP 3 Interrupt enable for TX endpoint 3 2 TX EP 2 Interrupt enable for TX endpoint 2 1 TX EP 1 Interrupt enable for TX endpoint 1 0 TX EP 0 Interrupt enable for TX endpoin...

Page 1873: ...X FIFO endpoint 14 29 TX FIFO 13 Interrupt enable for TX FIFO endpoint 13 28 TX FIFO 12 Interrupt enable for TX FIFO endpoint 12 27 TX FIFO 11 Interrupt enable for TX FIFO endpoint 11 26 TX FIFO 10 In...

Page 1874: ...s Bits Field Value Description 31 30 Reserved 0 Always read as 0 Writes have no effect 29 28 Tx15_mode 00 Transparent mode on TX endpoint 15 01 RNDIS MODE on TX endpoint 15 10 CDC mode on TX endpoint...

Page 1875: ...TX endpoint 6 11 Generic RNDIS mode on TX endpoint 6 9 8 Tx5_mode 00 Transparent mode on TX endpoint 5 01 RNDIS MODE on TX endpoint 5 10 CDC mode on TX endpoint 5 11 Generic RNDIS mode on TX endpoint...

Page 1876: ...Description 31 30 Reserved 0 Always read as 0 Writes have no effect 29 28 Rx15_mode 00 Transparent mode on RX endpoint 15 01 RNDIS MODE on RX endpoint 15 11 CDC mode on RX endpoint 15 10 Generic RNDIS...

Page 1877: ...11 Generic RNDIS mode on RX endpoint 6 9 8 Rx5_mode 00 Transparent mode on RX endpoint 5 01 RNDIS MODE on RX endpoint 5 10 CDC mode on RX endpoint 5 11 Generic RNDIS mode on RX endpoint 5 7 6 Rx4_mode...

Page 1878: ...tiple of the endpoint size The maximum value this register can be programmed with is 0x10000 or 65536 N can range from 1 to 15 The USB0 generic RNDIS EPn size register is shown in Figure 20 80 and des...

Page 1879: ...generate IN tokens until the end of the RNDIS packet For transparent mode every USB packet is an EOP CPPI packet so the auto req never functions and acts like auto req is disabled The USB0 auto req re...

Page 1880: ...Auto req on all but EOP 10 Reserved 11 Auto req always 13 12 Rx7_autoreq RX endpoint 7 Auto Req enable 00 No auto req 01 Auto req on all but EOP 10 Reserved 11 Auto req always 11 10 Rx6_autoreq RX en...

Page 1881: ...RP fix logic blocks the AVAID from the PHY to the OTG core This time allows the VBUS signal the ability to get below the thresholds and therefore remove the chance of voltage bounces which could give...

Page 1882: ...details The USB0 teardown register is shown in Figure 20 83 and described in Table 20 94 Figure 20 83 USB0 Teardown Register USB0TDOWN 31 17 16 15 1 0 tx_tdown Rsvd rx_tdown Rsvd R W 0h R 0h R W 0h R...

Page 1883: ...t R 0h R W 0h R W 1h R W 0h LEGEND R W Read Write R Read only n value after reset Table 20 95 USB0 PHY UTMI Register USB0UTMI Field Descriptions Bits Field Description 31 24 Reserved Always read as 0...

Page 1884: ...value after reset Table 20 96 USB0 MGC UTMI Loopback Register USB0UTMILB Field Descriptions Bits Field Description 31 29 Reserved Always read as 0 Writes have no effect 28 suspendm Loopback test obse...

Page 1885: ...gnals control the inputs to the PHY instead of the Mentor controller outputs The phy_test mode is not active with loopback mode is active When phy_test is active than the PHY inputs datainh is equal t...

Page 1886: ...ISEP2 USB1 Generic RNDIS Size EP2 1888h USB1GENRNDISEP3 USB1 Generic RNDIS Size EP3 188Ch USB1GENRNDISEP4 USB1 Generic RNDIS Size EP4 1890h USB1GENRNDISEP5 USB1 Generic RNDIS Size EP5 1894h USB1GENRND...

Page 1887: ...R 0h R 0h LEGEND R W Read Write R Read only n value after reset Table 20 99 USB1 Revision Register USB1REV Field Descriptions Bits Field Values Description 31 30 Scheme Used to distinguish between ol...

Page 1888: ...enabled 0 this allows additional time for the VBUS signal to be measured against the VBUS thresholds The time is specified in the USB1 SRP Fix Time Register 29 06 Reserved 0 Always read as 0 Writes h...

Page 1889: ...imizes software accesses in a module where a large number of events are associated to one IRQ line The merged status is read only and does not need to be actively cleared like the IRQ status It will c...

Page 1890: ...le after it has been written to The USB1 IRQ_EOI register is shown in Figure 20 91 and described in Table 20 103 Figure 20 91 USB1 IRQ_EOI Register USB1IRQEOI 31 1 0 EOI Reserved for USB1 R 0h R W 0h...

Page 1891: ...R W 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 20 104 USB1 IRQ_STATUS_RAW_0 Register USB1IRQSTATRAW1 Field Descriptions Bits Field Description 31 RX EP 15 Interrupt status f...

Page 1892: ...tatus for TX endpoint 7 6 TX EP 6 Interrupt status for TX endpoint 6 5 TX EP 5 Interrupt status for TX endpoint 5 4 TX EP 4 Interrupt status for TX endpoint 4 3 TX EP 3 Interrupt status for TX endpoin...

Page 1893: ...r USB1IRQSTATRAW1 Field Descriptions Bits Field Description 31 TX FIFO 15 Interrupt status for TX FIFO endpoint 15 30 TX FIFO 14 Interrupt status for TX FIFO endpoint 14 29 TX FIFO 13 Interrupt status...

Page 1894: ...terrupt status for SOF started 2 USB 2 Interrupt status for Reset signaling detected peripheral mode Babble detected host mode 1 USB 1 Interrupt status for Resume signaling detected 0 USB 0 Interrupt...

Page 1895: ...0h LEGEND R W Read Write R Read only n value after reset Table 20 106 USB1 IRQ_STATUS_0 Register USBIRQSTAT0 Field Descriptions Bits Field Description 31 RX EP 15 Interrupt status for RX endpoint 15...

Page 1896: ...s for TX endpoint 7 6 TX EP 6 Interrupt status for TX endpoint 6 5 TX EP 5 Interrupt status for TX endpoint 5 4 TX EP 4 Interrupt status for TX endpoint 4 3 TX EP 3 Interrupt status for TX endpoint 3...

Page 1897: ...1 Field Descriptions Bits Field Description 31 TX FIFO 15 Interrupt status for TX FIFO endpoint 15 30 TX FIFO 14 Interrupt status for TX FIFO endpoint 14 29 TX FIFO 13 Interrupt status for TX FIFO end...

Page 1898: ...upt status for SOF started 2 USB 2 Interrupt status for Reset signaling detected peripheral mode Babble detected host mode 1 USB 1 Interrupt status for Resume signaling detected 0 USB 0 Interrupt stat...

Page 1899: ...W 0h R W 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 20 108 USB1 IRQ_ENABLE_SET_0 Register USB1IRQENABLESET0 Field Descriptions Bits Field Description 31 RX EP 15 Interrupt e...

Page 1900: ...enable for TX endpoint 7 6 TX EP 6 Interrupt enable for TX endpoint 6 5 TX EP 5 Interrupt enable for TX endpoint 5 4 TX EP 4 Interrupt enable for TX endpoint 4 3 TX EP 3 Interrupt enable for TX endpoi...

Page 1901: ...gister USB1IRQENABLESET1 Field Descriptions Bits Field Description 31 TX FIFO 15 Interrupt enable for TX FIFO endpoint 15 30 TX FIFO 14 Interrupt enable for TX FIFO endpoint 14 29 TX FIFO 13 Interrupt...

Page 1902: ...nterrupt enable for SOF started 2 USB 2 Interrupt enable for Reset signaling detected peripheral mode Babble detected host mode 1 USB 1 Interrupt enable for Resume signaling detected 0 USB 0 Interrupt...

Page 1903: ...W 0h R W 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 20 110 USB1 IRQ_ENABLE_CLR_0 Register USB1IRQENABLECLR0 Field Descriptions Bits Field Description 31 RX EP 15 Interrupt...

Page 1904: ...enable for TX endpoint 7 6 TX EP 6 Interrupt enable for TX endpoint 6 5 TX EP 5 Interrupt enable for TX endpoint 5 4 TX EP 4 Interrupt enable for TX endpoint 4 3 TX EP 3 Interrupt enable for TX endpoi...

Page 1905: ...egister USB1IREENABLECLR1 Field Descriptions Bits Field Description 31 TX FIFO 15 Interrupt enable for TX FIFO endpoint 15 30 TX FIFO 14 Interrupt enable for TX FIFO endpoint 14 29 TX FIFO 13 Interrup...

Page 1906: ...nterrupt enable for SOF started 2 USB 2 Interrupt enable for Reset signaling detected peripheral mode Babble detected host mode 1 USB 1 Interrupt enable for Resume signaling detected 0 USB 0 Interrupt...

Page 1907: ...Value Description 31 30 Reserved 0 Always read as 0 Writes have no effect 29 28 Tx15_mode 00 Transparent Mode on TX endpoint 15 01 RNDIS MODE on TX endpoint 15 10 CDC Mode on TX endpoint 15 11 Generi...

Page 1908: ...11 Generic RNDIS Mode on TX endpoint 6 9 8 Tx5_mode 00 Transparent Mode on TX endpoint 5 01 RNDIS MODE on TX endpoint 5 10 CDC Mode on TX endpoint 5 11 Generic RNDIS Mode on TX endpoint 5 7 6 Tx4_mod...

Page 1909: ...Value Description 31 30 Reserved 0 Always read as 0 Writes have no effect 29 28 Rx15_mode 00 Transparent Mode on RX endpoint 15 01 RNDIS MODE on RX endpoint 15 10 CDC Mode on RX endpoint 15 11 Generi...

Page 1910: ...11 Generic RNDIS Mode on RX endpoint 6 9 8 Rx5_mode 00 Transparent Mode on RX endpoint 5 01 RNDIS MODE on RX endpoint 5 10 CDC Mode on RX endpoint 5 11 Generic RNDIS Mode on RX endpoint 5 7 6 Rx4_mod...

Page 1911: ...ed with a value that is an integer multiple of the endpoint size N can range from 1 to 15 The USB1 generic RNDIS EP N size register is shown in Figure 20 102 and described in Table 20 114 Figure 20 10...

Page 1912: ...ket For transparent mode every USB packet is an EOP CPPI packet so the auto req never functions and acts like auto req is disabled The USB1 auto req register is shown in Figure 20 103 and described in...

Page 1913: ...req on all but EOP 10 Reserved 11 Auto req always 13 12 Rx N 6 _autoreq RX endpoint N 6 Auto Req enable 00 No auto req 01 Auto req on all but EOP 10 Reserved 11 Auto req always 11 10 Rx N 5 _autoreq...

Page 1914: ...SRP fix logic blocks the AVAID from the PHY to the OTG core This time allows the VBUS signal the ability to get below the thresholds and therefore remove the chance of voltage bounces which could give...

Page 1915: ...details The USB1 teardown register is shown in Figure 20 105 and described in Table 20 117 Figure 20 105 USB1 Teardown Register USB1TDOWN 31 17 16 15 1 0 tx_tdown Rsvd rx_tdown Rsvd R W 0 R 0 R W 0 R...

Page 1916: ...e0ext R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only n value after reset Table 20 118 USB1 PHY UTMI Register USB1UTMI Field Descriptions Bits Field Description 31 24 Reserved Always read...

Page 1917: ...value after reset Table 20 119 USB1 MGC UTMI Loopback Register USB1UTMILB Field Descriptions Bits Field Description 31 29 Reserved Always read as 0 Writes have no effect 28 suspendm Loopback test obs...

Page 1918: ...als control the inputs to the PHY instead of the Mentor controller outputs The phy_test mode is not active with loopback mode is active When phy_test is active than the PHY inputs datainh is equal to...

Page 1919: ...Tx Channel 3 Global Configuration Register 2868h RXGCR3 Rx Channel 3 Global Configuration Register 286Ch RXHPCRA3 Rx Channel 3 Host Packet Configuration Register A 2870h RXHPCRB3 Rx Channel 3 Host Pa...

Page 1920: ...der to allocate a channel teardown descriptor from the teardown descriptor queue 11 0 td_desc_qnum This field controls which of the 2K queues in the indicated queue manager should be read in order to...

Page 1921: ...iguration Register TXGCRn Field Descriptions Bits Field Name Value Description 31 tx_enable This field enables or disables the channel 0 Channel is disabled 1 Channel is enabled This field will be cle...

Page 1922: ...hannel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the...

Page 1923: ...r A RXHPCRAn 31 30 29 28 27 16 Reserved rx_host_fdq1_qmgr rx_host_fdq1_qnum R 0h W W 15 14 13 12 11 0 Reserved rx_host_fdq0_qmgr rx_host_fdq0_qnum R 0h W W LEGEND R W Read Write R Read only n value af...

Page 1924: ...ead only n value after reset Table 20 128 Rx Channel N Host Packet Configuration Register B RXHPCRBn Field Descriptions Bits Field Name Description 31 30 Reserved Reserved 29 28 rx_host_fdq3_qmgr This...

Page 1925: ...0h LEGEND R W Read Write R Read only n value after reset Table 20 130 CPPI DMA Scheduler Control Register DMA_SCHED_CTRL Field Descriptions Bits Field Name Value Description 31 enable This is the enab...

Page 1926: ...l number given in the scheduler table entry 23 entry2_rxtx This bit indicates if this entry is for a Tx or an Rx channel and is encoded as follows 0 Tx Channel 1 Rx Channel 22 21 Reserved 0 Reserved 2...

Page 1927: ...a Tx entry the DMA will be presented with a scheduling credit for that exact Tx channel If this is an Rx entry the DMA will be presented with a scheduling credit for the Rx FIFO that is associated wit...

Page 1928: ...on Count Register 6 403Ch Qmgr Free Descriptor Buffer Starvation Count Register 7 4080h Qmgr Linking RAM Region 0 Base Address Register 4084h Qmgr Linking RAM Region 0 Size Register 4088h Qmgr Linking...

Page 1929: ...5 0 revmin Minor revision 20 9 5 2 Queue Manager Queue Diversion Register DIVERSION The queue manager queue diversion register DIVERSION is used to transfer the contents of one queue onto another que...

Page 1930: ...the CPPI DMA This field is cleared when read via the CPU 20 9 5 4 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 The queue manager free descriptor buffer starvation count reg...

Page 1931: ...e CPPI DMA This field is cleared when read via the CPU 20 9 5 6 Queue Manager Free Descriptor Buffer Starvation Count Register 3 FDBSC3 The queue manager free descriptor buffer starvation count regist...

Page 1932: ...the CPPI DMA This field is cleared when read via the CPU 20 9 5 8 Queue Manager Free Descriptor Buffer Starvation Count Register 5 FDBSC5 The queue manager free descriptor buffer starvation count reg...

Page 1933: ...the CPPI DMA This field is cleared when read via the CPU 20 9 5 10 Queue Manager Free Descriptor Buffer Starvation Count Register 7 FDBSC7 The queue manager free descriptor buffer starvation count reg...

Page 1934: ...Register LRAM0SIZE The queue manager linking RAM region 0 size register LRAM0SIZE is used to set the size of the array of linking pointers that are located in region 0 of linking RAM The size specifie...

Page 1935: ...set Table 20 145 Queue Manager Linking RAM Region 1 Base Address Register LRAM1BASE Field Descriptions Bits Field Name Description 31 0 region1_base This field stores the base address for the second r...

Page 1936: ...133 and described in Table 20 148 Figure 20 133 Queue Manager Queue Pending Register 2 PEND2 31 0 qpend2 R 0h LEGEND R W Read Write R Read only n value after reset Table 20 148 Queue Manager Queue Pe...

Page 1937: ...r The queue manager memory region R base address register QMEMRBASEr is written by the Host to set the base address of memory region R This memory region stores a number of descriptors of a particular...

Page 1938: ...rom 9 15 are reserved 7 3 Reserved Reserved 2 0 reg_size This field indicates the size of the memory region in terms of number of descriptors It is an encoded value that specifies region size as 2 5 r...

Page 1939: ...on this queue 20 9 5 23 Queue Manager Queue N Register C CTRLCn The queue manager queue N register C CTRLCn is used to provide additional information about the packet that is being pushed or popped fr...

Page 1940: ...yte increments with values 0 to 31 representing 24 and so on to 148 bytes This field returns a 0x0 when an empty queue is read 20 9 5 25 Queue Manager Queue N Status Register A QSTATAn The queue manag...

Page 1941: ...tions Bits Field Name Description 31 28 Reserved Reserved 27 0 queue_byte_count This field indicates how many bytes total are contained in all of the packets that are currently queued on this queue 20...

Page 1942: ...ters 120h 12Fh EP2 and so on Two instances of the mentor core registers exist within USB0 space Since both USB modules operate independent of each other each USB core has its own set of registers USB0...

Page 1943: ...R W Read Write R Read only n value after reset Table 20 162 Power Management Register USBn_POWER Field Descriptions Bits Field Name Description 7 ISOUPDATE When set the USB controller will wait for an...

Page 1944: ...1 0 EP15TX EP14TX EP13TX EP12TX EP11TX EP10TX EP9TX EP8TX EP7TX EP6TX EP5TX EP4TX EP3TX EP2TX EP1TX EP0 R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0...

Page 1945: ...RX EP13RX EP12RX EP11RX EP10RX EP9RX EP8RX EP7RX EP6RX EP5RX EP4RX EP3RX EP2RX EP1RX Rsvd R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0h...

Page 1946: ...X EP5TX EP4TX EP3TX EP2TX EP1TX EP0 R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h LEGEND R W Read Write R Read only n value after rese...

Page 1947: ...X EP6RX EP5RX EP4RX EP3RX EP2RX EP1RX Rsvd R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0 1h R 0h LEGEND R W Read Write R Read only n value after...

Page 1948: ...escription 7 VBUSERR Set when VBus drops below the VBus valid threshold during a session Only valid when the USB controller is A device All active interrupts will be cleared when this register is read...

Page 1949: ...e 6 SESSREQ Session request interrupt enable 5 DISCON Disconnect interrupt enable 4 CONN Connect interrupt enable 3 SOF Start of frame interrupt enable 2 RESET_BABBLE Reset interrupt enable 1 RESUME R...

Page 1950: ...map The index register for selecting the endpoint status and control registers is shown in Figure 20 154 and described in Table 20 170 Figure 20 154 Index Register for Selecting the Endpoint Status a...

Page 1951: ...nnected And if the FORCE_HOST but remains set it re enters Host mode next time the SESSION bit is set The operating speed is determined using the FORCE_HS and FORCE_FS bits 6 FIFO_ACCESS Set this bit...

Page 1952: ...USBn_TXMAXP The maximum packet size for peripheral host transmit endpoint register USBn_TXMAXP defines the maximum amount of data that can be transferred through the selected Tx endpoint in a single...

Page 1953: ...PEND Set this bit to clear the SETUPEND bit It is cleared automatically 6 SERV_RXPKTRDY Set this bit to clear the RXPKTRDY bit It is cleared automatically 5 SENDSTALL Set this bit to terminate the cur...

Page 1954: ...o this bit is ignored 8 FLUSHFIFO Write 1 to this bit to flush the next packet to be transmitted read from the Endpoint 0 FIFO The FIFO pointer is reset and the TXPKTRDY RXPKTRDY bit is cleared Note F...

Page 1955: ...ear the bit to enable it as Rx Note This bit has any effect only where the same endpoint FIFO is used for both Transmit and Receive transactions 12 DMAEN Set this bit to enable the DMA request for the...

Page 1956: ...et to be cleared from the FIFO regardless of whether an ACK was received This can be used by Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous endpoints 10 DMAMODE This...

Page 1957: ...ot exist The maximum packet size for peripheral host receive endpoint register is shown in Figure 20 161 and described in Table 20 178 Figure 20 161 Maximum Packet Size for Peripheral Host Receive End...

Page 1958: ...e point at which the FIFO becomes full Note This bit only has any effect in high speed mode in which mode it should be set for all Interrupt endpoints PID_ERROR Applies only for ISO Transactions The c...

Page 1959: ...ing the Rx DMA CPU Mode If the CPU sets the AUTOCLEAR bit then the RXPKTRDY bit will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the Receive FIFO When packets of less...

Page 1960: ...int is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RXINTERVAL register You should clear this bit to allow the endpoint to continue 2 ERROR The US...

Page 1961: ...et 20 9 6 2 10 Receive Count Register USBn_RXCOUNT The receive count register USBn_RXCOUNT is a 13 bit read only register that holds the number of received data bytes in the packet currently in line t...

Page 1962: ...is register is shown in Figure 20 166 and described in Table 20 183 Figure 20 166 Type Register Host mode only USBn_HOST_TYPE0 7 6 5 0 SPEED Reserved R W 0 3h R 0h LEGEND R W Read Write R Read only n...

Page 1963: ...pe Register Host mode only USBn_HOST_TXTYPE 7 6 5 4 3 0 SPEED PROT TENDPN R W 0 3h R W 0 3h R W 0 Fh LEGEND R W Read Write R Read only n value after reset Table 20 184 Transmit Type Register Host mode...

Page 1964: ...0 register is shown in Figure 20 168 and described in Table 20 185 Figure 20 168 NAKLimit0 Register Host mode only USBn_HOST_NAKLIMIT0 7 5 4 0 Reserved EP0NAKLIMIT R 0h R W 0 1Fh LEGEND R W Read Write...

Page 1965: ...nsmit Interval Register Host mode only USBn_HOST_TXINTERVAL Field Descriptions Bit Field Description For interrupt and isochronous transfers defines the polling interval for the currently selected tra...

Page 1966: ...egister Host mode only USBn_HOST_RXTYPE 7 6 5 4 3 0 SPEED PROT RENDPN R W 0 3h R W 0 3h R W 0 Fh LEGEND R W Read Write R Read only n value after reset Table 20 187 Receive Type Register Host mode only...

Page 1967: ...ter Host mode only USBn_HOST_RXINTERVAL Field Descriptions Bit Field Description For interrupt and isochronous transfers defines the polling interval for the currently selected transmit endpoint For b...

Page 1968: ...register needs to be set to zero Automatic splitting of bulk packets is not selected Automatic splitting of bulk packets is selected 5 BIGENDIAN Indicates endian ordering INDEX register needs to be s...

Page 1969: ...riting of multiple packets is not supported as flags need to be set after each packet is written Note 3 Following a STALL response or a Tx strike out error on dndpoint 1 15 the associated FIFO is comp...

Page 1970: ...cking for high speed chirps when the device is reset Only valid in Host mode 5 LSDEV This read only bit is set when a low speed device has been detected being connected to the port Only valid in Host...

Page 1971: ...s shown in Figure 20 175 and described in Table 20 193 Figure 20 175 Transmit Endpoint FIFO Size Register USBn_TXFIFOSZ 7 6 5 4 3 0 Reserved DPB SZ R 0h R 0 1h R 0 Fh LEGEND R W Read Write R Read only...

Page 1972: ...r is shown in Figure 20 176 and described in Table 20 194 Figure 20 176 Receive Endpoint FIFO Size Register USBn_RXFIFOSZ 7 6 5 4 3 0 Reserved DPB SZ 0h 0 1h 0 Fh LEGEND R W Read Write R Read only n v...

Page 1973: ...for the use of endpoint 0 Allocation of FIFO should exclude this reserved location The transmit endpoint FIFO address register is shown in Figure 20 177 and described in Table 20 195 Figure 20 177 Tra...

Page 1974: ...er USBn_RXFIFOADDR Field Descriptions Bit Field Description 15 13 Reserved Reserved 12 0 ADDR Start address of endpoint FIFO in units of 8 bytes If m ADDR then the start address is 8 m 20 9 7 2 6 Hard...

Page 1975: ...in host mode operation only that records the address of the target function that is to be accessed through the associated endpoint EPn USBn_ TXFUNCADDR needs to be defined for each Tx endpoint that is...

Page 1976: ...lators set to 0 if single transaction translator set to 1 if multiple transaction translators Note If endpoint 0 is connected to a hub then USBn_TXHUBADDRm need to be defined for this endpoint The tra...

Page 1977: ...ved 6 0 HUBPORT Port number of the hub 20 9 7 3 4 Receive Function Address Register USBn_RXFUNCADDRm The receive function address register USBn_RXFUNCADDRm is a 7 bit read write register meaningful in...

Page 1978: ...egister USBn_RXHUBADDRm Field Descriptions Bit Field Description 7 MULT_TRANS Set to 1 if hub has multiple transaction translators Cleared to 0 if only single transaction translator is available 6 0 H...

Page 1979: ...4h 10h m USBn_RXMAXPm See USBn_RXMAXP Reg Def 106h 10h m USBn_ PERI_RXCSRm See USBn_PERI_RXCSR Reg Def 108h USBn_COUNT0 See USBn_COUNT0 Reg Def 108h 10h m USBn_ RXCOUNTm See USBn_RXCOUNT Reg Def 10Fh...

Page 1980: ...Figure 20 186 CM_DEFAULT_L3_SLOW_CLKSTCTRL Register 31 9 8 7 2 1 0 Reserved CLKACTIVITY_USB_GCLK Reserved CLKTRCTRL R 0 R 0 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 20 20...

Page 1981: ...Bit 0 1 Bit Field Value Description Priv Else 31 9 Reserved 0 Reserved R O R O N A 8 PHYCLKSRC USB PHY reference clock source R W R O N A 0 Corresponding clock is gated 1 Corresponding clock is activ...

Page 1982: ...ield Descriptions Access Lock Bit 0 1 Bit Field Description Priv Else 31 Reserved Reserved R O R O N A 30 28 COMPDISTUNE Disconnect Threshold Adjust R W R O N A 27 23 Reserved Reserved R O R O N A 22...

Page 1983: ...ield Descriptions Access Lock Bit 0 1 Bit Field Description Priv Else 31 Reserved Reserved R O R O N A 30 28 COMPDISTUNE Disconnect Threshold Adjust R W R O N A 27 23 Reserved Reserved R O R O N A 22...

Page 1984: ...1984 Universal Serial Bus USB SPRUGX9 15 April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated...

Page 1985: ...rts up in secure mode The ROM Code takes care of early initialization The ROM code switches the device into public mode hence the Public ROM Code provides run time services for cache maintenance This...

Page 1986: ...upt ISR Interrupt Service Routine JTAG Joint Test Action Group This term is used to refer to the Debugging and Testing interface Kbps Kilobits per second KB Kilobyte 1024 B LPDDR2 Low Power Double Dat...

Page 1987: ...Booting Initial SW in this case called Downloaded SW in internal RAM Specific case of Peripheral Booting where the ROM Code mechanism is used to program external Pre Flashing Flash memories Primary P...

Page 1988: ...ers and hardware abstraction layer HAL One layer communicates with a lower level layer through a unified interface The high level layer is in charge of the main tasks of the Public ROM Code watchdog a...

Page 1989: ...as part of the public start up procedure The booting device list is created based on the MBOOT A booting device can be a memory booting device soldered flash memory or temporarily booting device like...

Page 1990: ...Figure 21 3 ROM Memory Map 21 3 1 1 Public ROM Exception Vectors Table 21 3 lists the Public ROM exception vectors The reset exception is redirected to the Public ROM Code startup Other exceptions are...

Page 1991: ...ion is located at address 200C0h In addition the function clears global cold reset status upon issuing the global SW reset Table 21 4 Dead Loops Address Purpose 20080h Undefined exception default hand...

Page 1992: ...e first seven addresses are ARM instructions which load the value located in the subsequent seven addresses into the PC register Theses instructions are executed when an exception occurs since they ar...

Page 1993: ...egister Then the ROM Code jumps to the data abort dead loop 2008Ch 21 3 2 4 Tracing Data Thissection contains trace vectors reflecting the execution path of the public boot Section 21 12 describes the...

Page 1994: ...0000h that is immediately next to the Secure ROM Code As shown at top of Figure 21 5 the CPU jumps to the Public ROM Code reset vector once it has completed the secure boot initialization Once in publ...

Page 1995: ...z The ROM Code configures the clocks and DPLLs that are necessary for ROM Code execution MAIN PLL locked to provide 220 MHz clocks for ARM and peripheral blocks DDR DPLL locked to provide 400 MHz for...

Page 1996: ...one of NOR NAND or SPI EEPROM The peripheral booting is executed when the booting device type is Ethernet PCIe or UART The memory booting procedure reads data from a memory type device If a valid boot...

Page 1997: ...d reserved reserved reserved 1011 reserved reserved reserved reserved 1100 reserved reserved reserved reserved 1101 reserved reserved reserved reserved 1110 GP Fast External Boot UART Ethernet GMII PC...

Page 1998: ...vector 0x0 routed to the GPMC This feature is fully driven by HW without any SW involvement In this configuration the MBOOT 15 signal selects whether the WAIT signal must be monitored on the GPMC inte...

Page 1999: ...s of a blind jump in ARM mode to a code located in an external XIP device connected to CS0 The jump is performed with minimum on chip ROM Code execution without configuring any PLL Allows the customer...

Page 2000: ...storage non XIP into internal RAM Failure in image copy results in memory booting returning to the main booting procedure that will select the next device for booting The next sections detail procedur...

Page 2001: ...connected to CS0 mapped to address 800 0000h Wait pin signal WAIT0 is monitored depending on the MBOOT configuration pins XIP XIPWAIT Depending on the MBOOT option the GPMC is configured to use the WA...

Page 2002: ...t of pins that are configured by the ROM in the case of NOR boot mode are listed in Table 21 10 Note that all the pins might not be driven at boot time The decision as to which pins need to be driven...

Page 2003: ...tore the Loaded Sector with Initial SW in the Target Buffer Initial SW Execution No Yes Preliminary www ti com Memory Booting Image Shadowing for non XIP memories Shadowing on the GP device The GP dev...

Page 2004: ...searched for an image The block size depends on device The initialization routine for NAND devices consists in three parts GPMC initialization device detection with parameters determination and final...

Page 2005: ...and the addressing mode The remaining data bytes from the parameters page stream are simply ignored Table 21 12 ONFI Parameters Page Description Offset Description Size bytes 6 Features supported 2 8...

Page 2006: ...x8 2048 4096 64 Gb CE x16 2048 4096 64 Gb AE x8 2048 4096 64 Gb BE x16 2048 4096 When the parameters are retrieved from the ROM table page size and block size is updated based on 4th byte of NAND ID...

Page 2007: ...om address offset 80h The format of this NAND geometry information is as follows Table 21 16 NAND Geometry Information on I2C EEPROM Information Byte address Upper nibble Lower nibble 80h Magic Number...

Page 2008: ...Device Ready No Yes Device Replied ONFI Yes Issue Read Parameters Page Command Extract NAND Parameters From Device Parameters Page Update Page Size Block Size ECC Correction for Devices 1Gb Wait for...

Page 2009: ...2nd page of each block Since the ROM Code is looking for an image in the first four blocks it must detect block validity status of these blocks Blocks which are detected as invalid are not accessed la...

Page 2010: ...CC is compared against ECC stored in the spare area for the corresponding page Depending on the page size the amount of ECC data bytes stored in the corresponding spare area is different Figure 21 15...

Page 2011: ...ord MSB LSB x8 x16 ECC D 12 52 ECC B 11 ECC B 12 13 ECC C 0 ECC C 1 ECC C 12 ECC D 0 ECC D 1 ECC D 2 20 21 26 ECC D 11 ECC D 12 14 ECC B 12 Preliminary www ti com Memory Booting Figure 21 15 ECC Data...

Page 2012: ...4 ECC C 25 27 39 Preliminary Memory Booting www ti com Figure 21 16 ECC Data Mapping for 4KB Page and 16b BCH Encoding 21 7 4 SD Cards 21 7 4 1 Overview The ROM code supports booting from SD cards in...

Page 2013: ...2 System Interconnection An SD card can be connected to the MMC1 interface typically through a card cage Notes It may be possible to design the system so that an eSD memory type is connected to MMC1...

Page 2014: ...procedure with FAIL This is detection procedure is shown in Figure 21 18 As previously mentioned the contents of an SD card may be formatted as raw binary or within a FAT filesystem eSD devices only...

Page 2015: ...the booting file FAT entries Some memory devices which support file systems can be formatted with or without MBR therefore the first task of the ROM Code is to detect whether or not the device is hol...

Page 2016: ...2 16 32 Partition Read Partition 1st Sector Is this FAT12 16 32 Partition Find Booting File in the Root Directory Buffers FAT entries in FAT Buffer Preliminary Memory Booting www ti com Figure 21 19 S...

Page 2017: ...Partition Table Entry see Table 21 19 01EEh 16 Partition Table Entry see Table 21 19 01FEh 2 Signature AA55h Table 21 19 Partition Entry Offset Length bytes Entry Description Value 0000h 1 Partition...

Page 2018: ...or not is described in Figure 21 20 The ROM Code first checks if the signature is present Each partition entry is checked If its type is set to 00h then all fields in the entry must be 00h The partit...

Page 2019: ...tion 21 7 4 7 2 FAT12 16 32 Boot Sector The FAT file system is made out of several parts Boot Sector which holds the BIOS Parameter Block BPB File Allocation Table FAT which describes the use of each...

Page 2020: ...16 0024h 1 BS_DrvNum Drive Number 0025h 1 BS_Reserved1 00h 0026h 1 BS_BootSig Extended Boot Signature 29h Indicates that the following 3 fields are present 0027h 4 BS_VolID Volume Serial Number 002Bh...

Page 2021: ...flash memories connected to the device e g in the case of initial flashing firmware update or servicing 21 8 2 Boot Image Location and Size The boot image is downloaded directly into internal RAM at...

Page 2022: ...4s Five retries 21 8 4 3 FTP RFC 1350 After a successful BOOTP completion the device initiates the TFTP download of the boot image into SRAM The device has the capability to reach TFTP server within t...

Page 2023: ...he tables below Only legacy interrupt A is enabled MSI is disabled The device is configured in the D0 power state The link and device capability is configured for maximum flexibility The PCIe settings...

Page 2024: ...n parity 1 stop bit and no flow control 21 8 6 2 Boot Image Download UART boot uses x modem client protocol to receive the boot image Utilities like hyperterm teraterm minicom can be used on the PC si...

Page 2025: ...Number of sub blocks ID Sub Block 7 Device identification information Secure Mode Sub Block 4 Secure identification data Public Id Sub Block 23 Public identification data generated by a Secure ROM ser...

Page 2026: ...a EMU Deice 0h GP Device Table 21 32 Root Key Hash Sub Block Offset Size bytes Value 23h 1 14h sub block ID 24h 1 15h sub block size 25h 1 1h fixed value 26h 32 XXh Root Key Hash EMU Device 0h GP Devi...

Page 2027: ...e The mandatory section of a boot image contains the software that will be loaded into the memory and executed An overview of the image formats is shown in Figure 21 24 Figure 21 24 Image Formats a GP...

Page 2028: ...evice Image Format Field non XIP device XIP device offset Size bytes Description offset Size 0000h 4 Size of the image Destination 0004h 4 Address where to store the image code entry point Image 0008h...

Page 2029: ...be imported in the Secure RAM The PRIMAPP section contains the PPA and its Certificate which must be imported in the Secure RAM Optionally the TOC may contain CH sections CHSETTINGS is a mandatory sec...

Page 2030: ...egister points to the Booting Parameters structure which contains various information about the booting execution Table 21 37 details this structure Table 21 37 Booting Parameters Structure Offset Fie...

Page 2031: ...rtup phase and updated all along the boot process There are two sets of tracing vectors The first set is the current trace information after cold or warm reset The second set holds a copy of trace vec...

Page 2032: ...te 2 6 USB USB VBUS valid 2 7 USB USB session valid 2 8 Reserved Reserved 2 9 Reserved Reserved 2 10 Reserved Reserved 2 11 Reserved Reserved 2 12 Memory Boot Memory booting trial 0 2 13 Memory Boot M...

Page 2033: ...d 3 13 Reserved Reserved 3 14 Reserved Reserved 3 15 Reserved Reserved 3 16 Reserved Reserved 3 17 Reserved Reserved 3 18 Peripheral Boot Peripheral booting device UART3 3 19 Reserved Reserved 3 20 Pe...

Page 2034: ...orized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parti...

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