Preliminary
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Registers
6.3.6 HDMI_PHY Register Descriptions
Table 6-243. HDMI_PHY Registers Summary
Address Offset
Acronym
Register Name
04h
TMDS_CNTL2
TMDS Control Register
08h
TMDS_CNTL3
TMDS Control Register
0Ch
BIST_CNTL
BIST Control Register
20h
TMDS_CNTL9
TMDS Control Register
6.3.6.1
TMDS_CNTL2
Table 6-244. TMDS_CNTL2 Field Descriptions
Bit
Field
Value
Description
Type
31-6
Reserved
0
Reserved
RO
5
OE
0
Output enable control. 0: output drivers of TMDS outputs are switched off by default. 1:
R/W
output drivers are switched on.
4
TERM_EN
0
Source termination enable control. Default= 0. 1: bus termination is active; driver must also
R/W
be enabled. 0: bus termination is switched off
3-2
Reserved
2h
Reserved
RO
1
Clkdetect
x
Clock detector output. clkdetect = 1, if clock > 2.5MHz (typ). clkdetect = 0, if clock < 2.5MHz R
(typ)
0
Rsen
x
Receiver sense output. 0: When receiver is disconnected. 1: When receiver is connected
R
6.3.6.2
TMDS_CNTL3
Table 6-245. TMDS_CNTL3 Field Descriptions
Bit
Field
Value
Description
Type
31-5
Reserved
5h
Reserved
RO
4-3
clkmult_ctl
1
Clock multiplication factor control. When clkmult_ctl[1:0] = 11: 4x 10: 2x 01: 1x (default) 00:
R/W
0.5x Use this setting when pixel repetition is needed. Output clock “m_clkout_dig” depends
on “dpcolor_ctl” and “clkmult_ctl” bits. For example, say the input clock frequency “p_clkin”
is 30Mhz. dpcolor_ctl = 2’b10; clkmult_ctl = 2’b11 m_clkout_dig = 30 x 1.5 x 4 = 180Mhz
dpcolor_ctl = 2’b01; clkmult_ctl = 2’b11 m_clkout_dig = 30 x 1.25 x 4 = 150Mhz dpcolor_ctl
= 2’b00; clkmult_ctl = 2’b11 m_clkout_dig = 30 x 1.0 x 4 = 120Mhz etc..
2-1
dpcolor_ctl
0
Deep color mode control. When dpcolor_ctl[1:0] 11: invalid 10: 12 bit/channel 01: 10
R/W
bit/channel 00: 8 bit/channel (default)
0
pdb
1
Powerdown Control default = 1’b1; No power down 1’b0 : Phy will be power down
R/W
843
SPRUGX9 – 15 April 2011
High-Definition Multimedia Interface (HDMI)
© 2011, Texas Instruments Incorporated