Preliminary
Basic Programming Model
www.ti.com
After the return of the relevant IRQ/FIQ subroutine handle:
1. Disable IRQs/FIQs at ARM side.
2. Restore the INTCPS_THRESHOLD PRIORITYTHRESHOLD field.
3. Restore the ARM critical context registers.
The following sample code shows the three previous steps:
CAUTION
The following code is an assembly code compatible with ARM architecture
V6 and V7. This code is developed for the Texas Instruments Code
Composer Studio tool set. It is a draft version, only tested on an emulated
environment.
IRQ_ISR_end:
; Step 1 : Read-modify-write the CPSR to disable IRQs/FIQs at ARM side
MRS R0, CPSR ; Read the CPSR
ORR R0, R0, #0x80/0x40 ; Set the I/F bit
MSR CPSR, R0 ; Write it back to disable IRQs
; Step 2 : Restore the INTCPS_THRESHOLD register from R12
LDR R0, INTCPS_THRESHOLD_ADDR
STR R12, [R0]
; Step 3 : Restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and Link register
; Return after handling the interrupt
SUBS PC, LR, #4
shows the nested IRQ/FIQ processing sequence from the originating device peripheral
module to the main program interruption.
914
Interrupt Controller
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated