Local host or
DMA access
cmd
SDMAWREQN
dat0
Buffer Level
Command
Data
Time
Buffer full
Buffer empty
BLEN
bytes
LH sends a
write command
DMA write access
(BLEN writes)
From host
to card
From card
to host
From host
to card
Write transfer active
SD_PSTATE[8]
WTA = 1
Request cleared
after first DMA
access
Data fully written
in the card
Data to be sent to
the card is fully
written in the buffer
Busy
Data
From card
to host
From host
to card
Response
Interrupt request
Command
complete IRQ
Transfer
complete IRQ
CRC
status
Data
dat[3:1]
Preliminary
www.ti.com
Architecture
9.2.5.1.2 DMA Transmit Mode
In a DMA block write operation (single or multiple), the request signal SDMAWREQN is asserted to its
active level when a complete block is to be written to the buffer. The block size transfer is specified in
the SD_BLK[10:0] BLEN field.
The SDMAWREQN signal is deasserted to its inactive level when the sDMA has written one single
word to the buffer.
Only one request is sent per block; the DMA controller can make a 1-shot write access or multiple write
DMA bursts, in which case the DMA controller must manage the number of burst accesses, according
to block size BLEN field.
New DMA requests are internally masked if the sDMA has not written exactly BLEN bytes (as DMA
accesses are in 32-bit, then the number of sDMA read is Integer(BLEN/4)+1) and if there is not enough
memory space to write a complete block in the buffer.
provides a summary:
•
DMA transfer size = BLEN buffer size in one shot or by burst
•
One DMA request per block
Figure 9-10. DMA Transmit Mode
941
SPRUGX9 – 15 April 2011
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated