Logic inside PRCM
/F
SYSCLK24 (To EMAC (125 MHz))
Flying adder
synthesizer 5
Main pll clock 5
27 MHz
FREQ_5
/4
/72
432 MHz reference clock
for audio PLL
24 MHz clock for USB
27 MHz
/P
PFD
CP
VCO
/N
Flying adder
synthesizer 4
SYSCLK4 (To L3 interconnect and IPs (–500 MHz))
SYSCLK5 (To L3 interconnect,
L4 speed interconnect and IPs (–250 MHz))
SYSCLK6 (L4 standard interconnect and IPs (–125 MHz))
SYSCLK7
/A
/4
/2
/V
Main pll clock 4
27 MHz
FREQ_4
Flying adder
synthesizer 2
Main pll clock 2
27 MHz
FREQ_2
/C
/D
SYSCLK2 (To Cortex-A8 (~1 GHz MHz))
SYSCLK23 (To SGX530 (max 333 MHz))
/E
SYSCLK1 (To DSP (~1GHz))
Flying adder
synthesizer 1
Main pll clock 1
27 MHz
FREQ_1
Preliminary
Device Clocking and Flying Adder PLL
www.ti.com
4. AUDIO PLL
1.10.3.1.1 Main PLL
shows structure of Main PLL. The Main PLL has 5 flying adder synthesizers connected to the
multi-phase PLL. The outputs of these synthesizers are muxed with the 27 MHz reference clock to allow
its selection during PLL bypass mode.
lists the IPs that are clocked from each of these flying
adder synthesizers.
As shown in
, there are five independently controllable clock outputs (asynchronous to each
other) driven by the main PLL. The FREQ and post divider can be tuned independently to control each
clock. This makes it possible to run DSP, Cortex-A8 and interconnect independent of each other. However
as the same multiphase PLL is used to generate all these clocks, the choice of possible frequencies will
be limited. The set of available frequencies will depend upon choice of P and N for the multi phase PLL.
The Main PLL also provides a 432 MHz reference clock for the Audio PLL using a fixed divider. It is
assumed that the Main PLL will be locked at 1712 MHz to generate all the required clocks.
shows an example for Main PLL System Clock generation.
lists the divide ratios supported in
PRCM for each of the divider in Main PLL.
Figure 1-69. Main PLL Structure
Table 1-71. MAIN PLL Dividers
Divider
Supported Divide Ratios
Default Value
A
1/1, 1/2
1/1
C
1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8
1/1
D
1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8
1/4
E
1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8
1/1
V
1/5, 1/6, 1/8, 1/16
1/5
F
1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8
1/1
188 Chip Level Resources
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated