Preliminary
Control Module
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1.16.1.2.16 DDR PLL Frequency 2 Register (DDRPLL_FREQ2)
The DDRPLL_FREQ2 register is used to control the DDR PLL Clock 2 pre-divider frequency of the
SYSCLK9 (16 MHz - VTP) and SYSCLK10 (48 MHz - UART, SPI, CEC, etc.) clock. The default FREQ2
value is 8.85.
The DDR PLL Frequency 2 Register (DDRPLL_FREQ2) is shown in
and described in
.
Figure 1-131. DDR PLL Frequency 2 Register (DDRPLL_FREQ2)
31
30
29
28
27
24 23
0
DDR_LDFREQ2
Reserved
DDR_TRUNC2
DDR_INTFREQ2
DDR_FRACFREQ2
R/W-1
R-0
R/W-0
R/W-8h
R/W-D99999h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-171. DDR PLL Frequency 2 Register (DDRPLL_FREQ2) Field Descriptions
Bit
Field
Value
Description
31
DDR_LDFREQ2
1-0
Load Synth2 FREQ value. Setting this bit to 1 causes the INTFREQ and
FRACFREQ values to be loaded into DDR Synthesizer2.
30-29
Reserved
0
Reserved. Read returns 0.
28
DDR_TRUNC2
1-0
Synth2 Enable Truncate Correction
27-24
DDR_INTFREQ2
0-Fh
Synth2 Frequency integer divider.
23-0
DDR_FRACFREQ2
0-FF FFFFh
Synth2 Frequency fractional divider.
1.16.1.2.17 DDR PLL Divider 2 Register (DDRPLL_DIV2)
The DDRPLL_DIV2 register is used to control the DDR PLL Clock 2 post-divider frequency of the
SYSCLK9 (VTP), and SYSCLK10 (UART, SPI, CEC, etc.) clocks. The default DIV2 value is 30.
The DDR PLL Divider 2 Register (DDRPLL_DIV2) is shown in
and described in
Figure 1-132. DDR PLL Divider 2 Register (DDRPLL_DIV2)
31
9
8
7
0
Reserved
DDR_LDMDIV2
DDR_MDIV2
R-0
R/W-1
R/W-1Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-172. DDR PLL Divider 2 Register (DDRPLL_DIV2) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved. Read returns 0.
8
DDR_LDMDIV2
1-0
Load Synth2 M Divider value. Setting this bit to 1 causes the M Divider value to be loaded
into DDR Synthesizer2.
7-0
DDR_MDIV2
0-FFh
Synth2 Frequency M Post Divider.
284
Chip Level Resources
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated