clk
cmd
S
Data
+ CRC
E
dat0
Host ACMD12 Margin
S
ACMD12
Ncrc in Range
2 to 8 Cycles
S
CRC
Status
E
E
Preliminary
Architecture
www.ti.com
9.2.9 Auto Command 12 Timings
With the UHS definition of SD cards with higher frequency for clocks up to 208, SD standard imposes a
specific timing for Auto CMD12 "end bit" arrival.
9.2.9.1
Auto Command 12 Timings During Write Transfer
A margin named Ncrc in range of 2 to 8 cycles has been defined for SDR50 and SDR104 card
components for write data transfers, as auto command 12 'end bit' shall arrive after the CRC status
"end bit".
shows auto CMD12 timings during write transfer.
Figure 9-19. Auto CMD12 Timing During Write Transfer
The Host controller has a margin of 18 clock cycles to make sure that auto CMD12 'end bit' arrives after
the CRC status. This margin does not depend on bus configuration, DDR or standard transfer, 1,4 or 8
bus width.
950
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
