Preliminary
Architecture
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Table 3-2. EMAC and MDIO Signals for GMII Interface
Signal
Type
Description
EMAC_TXCLK
I
Transmit clock (EMAC_TXCLK). The transmit clock is a continuous clock that provides the timing
reference for transmit operations in 10/100 Mbps mode. The EMAC_TXD and EMAC_TXEN signals
are tied to this clock when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5 MHz
at 10 Mbps operation, and 25 MHz at 100 Mbps operation.
EMAC_GMTCLK
O
GMII source asynchronous transmit clock (EMAC_GMTCLK). This clock is used in 1000 Mbps mode
only, providing a continuous 125 MHz frequency for transmit operations. The EMAC_TXD and
EMAC_TXEN signals are tied to this clock when in Gigabit mode. The clock is generated by the
EMAC and is 125 MHz.
EMAC_TXD[0-7]
O
Transmit data (EMAC_TXD). The transmit data pins are a collection of 8 data signals comprising 8
bits of data. EMAC_TXD[0] is the least-significant bit (LSB). The signals are synchronized by
EMAC_TXCLK in 10/100 Mbps mode, and by EMAC_GMTCLK in Gigabit mode, and valid only
when EMAC_TXEN is asserted.
EMAC_TXEN
O
Transmit data enable (EMAC_TXEN). The transmit data enable signal indicates that the EMAC_TXD
pins are generating nibble data for use by the PHY. It is driven synchronously to EMAC_TXCLK in
10/100 Mbps mode, and to EMAC_GMTCLK in Gigabit mode.
EMAC_COL
I
Collision detected (EMAC_COL). The EMAC_COL pin is asserted by the PHY when it detects a
collision on the network. It remains asserted while the collision condition persists. This signal is not
necessarily synchronous to EMAC_TXCLK nor EMAC_RXCLK. This pin is used in half-duplex
operation only.
EMAC_CRS
I
Carrier sense (EMAC_CRS). The EMAC_CRS pin is asserted by the PHY when the network is not
idle in either transmit or receive. The pin is deasserted when both transmit and receive are idle. This
signal is not necessarily synchronous to EMAC_TXCLK nor EMAC_RXCLK. This pin is used in
half-duplex operation only.
EMAC_RXCLK
I
Receive clock (EMAC_RXCLK). The receive clock is a continuous clock that provides the timing
reference for receive operations. The EMAC_RXD, EMAC_RXDV, and EMAC_RXER signals are
tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation, 25 MHz
at 100 Mbps operation and 125 MHz at 1000 Mbps operation.
EMAC_RXD[0-7]
I
Receive data (EMAC_RXD). The receive data pins are a collection of 8 data signals comprising 8
bits of data. EMAC_RXD[0] is the least-significant bit (LSB). The signals are synchronized by
EMAC_RXCLK and valid only when EMAC_RXDV is asserted.
EMAC_RXDV
I
Receive data valid (EMAC_RXDV). The receive data valid signal indicates that the EMAC_RXD pins
are generating nibble data for use by the EMAC. It is driven synchronously to EMAC_RXCLK.
EMAC_RXER
I
Receive data error (EMAC_RXER). The receive data error signal is asserted for one or more
EMAC_RXCLK periods to indicate that an error was detected in the received frame. This is
meaningful only during data reception when EMAC_RXDV is active.
MDIO_MCLK
O
Management data serial clock (MDIO_MCLK). The MDIO data serial clock is sourced by the MDIO
module on the system. It is used to synchronize MDIO data access operations done on the
MDIO_MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control
register (CONTROL).
MDIO_MDIO
I/O
Management data input/output (MDIO_MDIO). The MDIO_MDIO pin drives PHY management data
into and out of the PHY by way of an access frame consisting of start of frame, read/write indication,
PHY address, register address, and data bit cycles. The MDIO_MDIO pin acts as an output for
everything except the data bit cycles, when the pin acts as an input for read operations.
412
EMAC/MDIO Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated