Preliminary
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Registers
6.3.5.17 CEC_INIT_ENABLE_0
Table 6-234. CEC_INIT_ENABLE_0 Field Descriptions
Bit
Field
Value
Description
Type
31-6
Reserved
0
Reserved
RO
5
CEC_INTR1_MASK5
Tx: Transmit Buffer Full/Empty Change event
R/W
0
Disable
1
Enable
4-3
Reserved
0
Reserved
RO
2
CEC_INTR1_MASK2
Transmitter FIFO Empty Event
R/W
0
Disable
1
Enable
1
CEC_INTR1_MASK1
Receiver FIFO Not Empty Event
R/W
0
Disable
1
Enable
0
CEC_INTR1_MASK0
Command Being Received Event
R/W
0
Disable
1
Enable
6.3.5.18 CEC_INIT_ENABLE_1
Table 6-235. CEC_INIT_ENABLE_1 Field Descriptions
Bit
Field
Value
Description
Type
31-4
Reserved
0
Reserved
RO
3
CEC_INTR2_MASK3
Rx FIFO Overrun Error Event
R/W
0
Disable
1
Enable
2
CEC_INTR2_MASK2
Short Pulse Detected Event
R/W
0
Disable
1
Enable
1
CEC_INTR2_MASK1
Frame Retransmit Count Exceeded Event
R/W
0
Disable
1
Enable
0
CEC_INTR2_MASK0
Start Bit Irregularity Event
R/W
0
Disable
1
Enable
839
SPRUGX9 – 15 April 2011
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