Media Controller
DDR
DDR
DDR
DDR
DDR
DDR
MBX1_U0_A8
MBX1_U1_64x
MBX1_U2_VPSSM3
MBX1_U3_VideoM3
Interrupt
MBX1
MBX_VPSSM3_A8
MBX_A8_VideoM3
MBX_VideoM3_A8
MBX_A8_64x
MBX_64x_A8
MBX_64x_VPSSM3
MBX_VPSSM3_64x
MBX_64x_VideoM3
MBX_VideoM3_64x
MBX_VPSSM3_VideoM3
MBX_VideoM3_VPSSM3
MBX_A8_VPSSM3
Shared
Memory
C674x
A8
Video M3
VPSS M3
Preliminary
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Inter-Processor Communication
1.12.3.1 System IPCs
depicts how Mailbox 1 (MBX1) will be used for system IPCs. 4 interrupts are generated from
the mailbox that allows the A8, C674x™, VPSS M3, and Video M3 to communicate. DDR is used as the
shared memory interface. An IPC can be created between any of the processors listed. The A8 will
communicate to the Video M3 and VPSS M3 using SysLink.
Figure 1-76. System IPCs
207
SPRUGX9 – 15 April 2011
Chip Level Resources
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