Preliminary
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1.10.3
Flying Adder PLL
...............................................................................................
1.10.4
Clock Out
.......................................................................................................
1.11
Bus Interconnect
.........................................................................................................
1.11.1
Terminology
.....................................................................................................
1.11.2
L3 Interconnect
.................................................................................................
1.12
Inter-Processor Communication
.......................................................................................
1.12.1
Reset Requirements
...........................................................................................
1.12.2
Features
.........................................................................................................
1.12.3
Overview and Strategy
........................................................................................
1.12.4
IPC Component Configuration
...............................................................................
1.13
Mailbox
....................................................................................................................
1.13.1
Overview
........................................................................................................
1.13.2
System Mailbox Integration
...................................................................................
1.13.3
Functional Description
.........................................................................................
1.13.4
Programming Guide
...........................................................................................
1.13.5
Mailbox Registers
..............................................................................................
1.14
Spinlock
...................................................................................................................
1.14.1
Overview
........................................................................................................
1.14.2
Integration
.......................................................................................................
1.14.3
Functional Description
.........................................................................................
1.14.4
Programming Guide
...........................................................................................
1.14.5
Spinlock Registers
.............................................................................................
1.15
Error Location Module
...................................................................................................
1.15.1
Error Location Module Overview
.............................................................................
1.15.2
ELM Integration
................................................................................................
1.15.3
ELM Functional Description
..................................................................................
1.15.4
ELM Basic Programming Model
.............................................................................
1.15.5
ELM Registers
..................................................................................................
1.16
Control Module
...........................................................................................................
1.16.1
Registers
........................................................................................................
1.17
Interrupt Controller
.......................................................................................................
1.18
Resets
.....................................................................................................................
2
DMM/TILER
.....................................................................................................................
2.1
Introduction
...............................................................................................................
2.1.1
Overview
.........................................................................................................
2.1.2
Features
..........................................................................................................
2.1.3
Functional Block Diagram
......................................................................................
2.1.4
Terminologies and Acronyms Used in this Document
.....................................................
2.2
Architecture
...............................................................................................................
2.2.1
DMM Functional Description
..................................................................................
2.2.2
TILER Functional Description
.................................................................................
2.3
Use Case
..................................................................................................................
2.3.1
DMM Basic Register Setup
....................................................................................
2.3.2
Simple LUT Bypass Use Case: Arrangement of Video Buffers
...........................................
2.3.3
LUT Refill Using the PAT Refill Engines
.....................................................................
2.3.4
Address Management Using LISA Sections
................................................................
2.4
Registers
..................................................................................................................
2.4.1
DMM Revision Register: DMM_REVISION
..................................................................
2.4.2
DMM Clock Management Configuration: DMM_SYSCONFIG
............................................
2.4.3
LISA Configuration Locking Register: DMM_LISA_LOCK
.................................................
2.4.4
DMM LISA MAP Registers: DMM_LISA_MAP_0-DMM_LISA_MAP_3
..................................
2.4.5
DMM TILER Orientation Registers: DMM_TILER_OR0-DMM_TILER_OR1
............................
2.4.6
DMM PAT Configuration Register: DMM_PAT_CONFIG
..................................................
4
Contents
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated