48 bits length
0
0
1
CRC
Content
136 bits length
0
0
1
CRC
Content
Preliminary
Architecture
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Coding Scheme for Response Token
Response packets always start with 0 and end with a 1. The second bit is a transmitter bit0 for a card
response. The content is different for each type of response (R1, R2, R3, R4, R5, and R6) and the
content is protected by 7-bit CRC checksum. Depending on the type of commands sent to the card, the
SD_CMD register must be configured differently to avoid false CRC or index errors to be flagged on
command response (see
). For more details about response types, see the SD Memory Card
Specification, or the SDIO Card Specification.
Table 9-2. Response Type Summary
(1)
Response Type
Index Check Enable
CRC Check Enable
SD_CMD[17:16]
SD_CMD[20]
SD_CMD[19]
RSP_TYPE
CICE
CCCE
Name of Response Type
00
0
0
No Response
01
0
1
R2
10
0
0
R3 (R4 for SD cards)
10
1
1
R1, R6, R5 (R7 for SD cards)
11
1
1
R1b, R5b
(1)
The SD/SDIO host controller assumes that both clocks may be switched off, whatever the value set in the SD_SYSCONFIG[9:8]
CLOCKACTIVITY bit.
and
depict the 48-bit and 136-bit response packets.
Figure 9-4. 48-Bit Response Packet (R1, R3, R4, R5, R6)
Figure 9-5. 136-Bit Response Packet (R2)
932
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated