Preliminary
Peripheral Booting
www.ti.com
Table 21-24. PCIe 64 BAR Window Size Configuration
PCIe64
BAR0/1
BAR 2/3
BAR 4/5
CS0WAIT :CS0BW
Size
CS0MUX[1:0]
Size
4KB
0
0
0
0
1
8MB
1
64MB
10
64MB
10
128MB
11
128MB
11
256MB
Table 21-25. PCIe BAR Window Base Address and Offset Configuration
BAR
Base Address
Offset
Comments
0
0000 0000h
0000 0000h
1 (64bit BAR0)
8080 0000h
4040 0000h
OCMC RAM1
2
8100 0000h
0800 0000h
GPMC
3 (64 Bit BAR2)
8180 0000h
8000 0000h
DDR 0
4
8200 0000h
C000 0000h
DDR 1
Note that the Base Address and Offset configurations can be changed from the host after the
enumeration is complete.
21.8.6 UART Boot Procedure
21.8.6.1 Device Initialization
•
UART boot uses UART0
•
UART0 is configured to run at 115200 baud, 8-bits, even parity, 1 stop bit and no flow control.
21.8.6.2 Boot Image Download
•
UART boot uses x-modem client protocol to receive the boot image.
•
Utilities like hyperterm, teraterm, minicom can be used on the PC side to download the boot image
to the board
•
With x-modem packet size of 1K throughout is roughly about 4KBytes/Sec.
•
The ROM code will ping the host 10 times in 3s to start x-modem transfer. If host does not respond,
UART boot will timeout.
•
Once the transfer has started, if the host does not send any packet for 3s, UART boot will time out
•
If the delay between two consecutive bytes of the same packet is more than 2ms, the host is
requested to re-transmit the entire packet again
•
Error checking using the CRC-16 support in x-modem. If an error is detected, the host is requested
to re-transmit the packet again
2024
ROM Code Memory and Peripheral Booting
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated