Preliminary
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20.9.1
USBSS Registers
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20.9.2
USB0 and USB1 Controller Registers
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20.9.3
CPPI DMA Controller Registers
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20.9.4
CPPI DMA Scheduler Registers
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20.9.5
CPPI DMA Queue Manager Registers
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20.9.6
USB Mentor Core Registers
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20.9.7
FIFOs
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20.9.8
USB Related Clock/PHY Control Registers
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21
ROM Code Memory and Peripheral Booting
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21.1
Introduction
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21.1.1
Device Types
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21.1.2
Acronyms and Naming Conventions
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21.2
Overview
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21.2.1
Architecture
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21.2.2
Functionality
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21.3
Memory Map
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21.3.1
Public ROM Memory Map
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21.3.2
Public RAM Memory Map
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21.4
Startup and Configuration
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21.4.1
ROM Code Start-up
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21.4.2
CPU State at Public Startup
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21.4.3
Clocking Configuration
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21.5
Booting
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21.5.1
Overview
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21.5.2
Device List
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21.6
Fast Internal Booting
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21.6.1
Overview
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21.6.2
External Booting
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21.7
Memory Booting
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21.7.1
Overview
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21.7.2
XIP Memory
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21.7.3
NAND
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21.7.4
SD Cards
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21.8
Peripheral Booting
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21.8.1
Overview
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21.8.2
Boot Image Location and Size
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21.8.3
Peripheral Boot Procedure Overview
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21.8.4
Ethernet Boot Procedure
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21.8.5
PCIe Boot Procedure
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21.8.6
UART Boot Procedure
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21.9
Image Format
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21.9.1
Overview
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21.9.2
Table of Contents
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21.10
Image Execution
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21.10.1
Overview
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21.10.2
Execution
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21.11
Services for HLOS Support
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21.12
Tracing
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21
SPRUGX9 – 15 April 2011
Contents
© 2011, Texas Instruments Incorporated